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| ddr3 (l) 2 gb sdram nt5c b( c ) 256 m8 f n / nt5cb(c) 128 m16 f p version 1. 6 1 nanya technology cooperation ? 0 4 / 201 4 all rights reserved. commercial, industrial and automotive ddr3(l) 2 gb sdram ? jedec ddr3 compli ant - 8n prefetch architecture - differential c lock (ck/ ?? ) and data strobe(dqs/ ??? ) - double - data rate on dqs, dqs and dm ? data integrity - auto self refresh ( a sr) by dram built - in t s - auto refresh and self refresh mode s ? power saving mode - partial array self refresh (pasr) 1 - power down mode ? cas latency (5/6/7/8/9/ 10 / 11 /12/13/14) ? cas write latency (5/6/7/8/9/10) ? additive latency ( 0 / cl - 1 / cl - 2 ) ? write recovery time (5/6/7/8/10/12/14/16) ? burst type ( sequential/i nterleave d) ? burst length (bl8/bc4/bc4 or 8 on the fly) programmable functions ? self refreshtemperature range(normal/extended) ? output driver impedance (34/40) ? on - die termination of rtt_nom(2 0/30/40/60/120) ? on - die termination of rtt_wr(60/120) ? precharge power down (slow/fast) ? signal integrity - configurable ds for system compatibility - configurable on - die termination - zq calibration for ds/odt impedance accuracy via external zq pad (240 ohm 1%) ? signal synchronization - write leveling via mr settings 7 - read leveling via mpr ? interface an d power supply - sstl_15 for ddr3:vdd/vddq= 1.5v ( 0.075v ) - sstl_135 4 for ddr3l:vdd/vddq= 1.35v ( - 0.067/+0.1v ) features density and addressing organization 256 m b x 8 128 m b x 16 bank address ba0 C ba2 ba0 C ba2 auto precharge a10 / ap a10 / ap bl switch on the fly a12 / ?? a12 / ?? row address a0 C a1 4 a0 C a1 3 column address a0 C a9 a0 C a9 page siz e 1kb 2 kb trefi( u s ) 5 t c <= 8 5 : 7.8 , t c >8 5 : 3 . 9 trfc(ns) 6 1 60ns packages / density information lead - free rohs compliance and halogen - fre e 2 gb ( org. / package) length x width (mm) ball pitch (mm) 256 m b x 8 78 - ball t fbga 8 .00 x 10.50 0.80 128 m b x 16 96 - ball t fbga 9. 00 x 13.00 0.80 ? speed grade (cl - trcd - trp) 2,3 - 2133 mbps / 14 - 14 - 14 - 1866 mbps / 12 - 12 - 12, 13 - 13 - 13 - 1600 mbps / 11 - 11 - 11 options nanya technology corp. nt5cb (c) 256m 8 f n / nt5cb (c) 128m16 f p ntc has the rights to change any specifications or product without notification. ? temperature range ( t c ) 5 - commercial grade = 0 ~ 95 - industrial grade ( - i ) = - 40 ~ 9 5 - automotive grade 2 ( - h ) = - 40 ~ 10 5 - automotive grade 3 ( - a ) = - 40 ~ 9 5 n ote 1 default state of pasr is disabed. this is enabled by using an electrical fuse. please contact with ntc for the demand. n ote 2 the timing specification of high speed bin is b ackward compatible with low speed bin . n ote 3 p lease refer to ordering information for the deailts (ddr3, ddr3l, ddr3l rs) . n ote 4 sstl_135 compatible to sstl_15 . that means 1.35v ddr3l are backward compatible to 1.5v ddr3 parts. 1.35v ddr3l - rs parts are exceptional and unallowable to be compatible to 1.35v ddr3l and 1.5v ddr3 parts. n ote 5 if t c exceeds 85c, the dram must be refreshed externally at 2x refresh, which is a 3.9us interval refresh rate. e xtended srt or asr must be enabled. n ote 6 violatin g trfc specification will induce malfunction. n ote 7 only support prime dq s feedback for each byte lane.
ddr3 (l) 2 gb sdram nt5c b( c ) 256 m8 f n / nt5cb(c) 128 m16 f p version 1. 6 2 nanya technology cooperation ? 0 4 / 201 4 all rights reserved. fundamental ac specifications C core timing ddr3 - 2133, ddr3 (l) - 1866, ddr3(l) - 1600 and ddr3(l) - 1333 speed bins ddr3 - 2133 ddr3 (l) - 1866 ddr3(l) - 1600 ddr3(l) - 1333 unit 14 - 14 - 14 12 - 12 - 12 13 - 13 - 13 1 1 - 11 - 11 9 - 9 - 9 10 - 10 - 10 parameter min max min max min max min max min max min max taa 13.09 20 12.84 20.0 13.91 20 13.75 20 13.5 20 15 20 ns trcd 13.09 - 12.84 - 13.91 - 13.75 - 13.5 - 15 - ns trp 13.09 - 12.84 - 13.91 - 13.75 - 13.5 - 15 - ns trc 46 .09 - 46.84 - 47.91 - 48.75 - 49.5 - 51 - ns tras 33 9*trefi 34.0 9*trefi 34 9*trefi 35 9*trefi 36 9*trefi 36 9*trefi ns ddr3(l) - 1066 and ddr3(l) - 800 speed bins ddr3(l) - 1066 ddr3(l) - 800 unit 7 - 7 - 7 8 - 8 - 8 5 - 5 - 5 6 - 6 - 6 parameter min max min max min ma x min max taa 13.125 20 15 20 12.5 20 15 20 ns trcd 13.125 - 15 - 12.5 - 15 - ns trp 13.125 - 15 - 12.5 - 15 - ns trc 50.625 - 52.5 - 50 - 52.5 - ns tras 37.5 9*trefi 37.5 9*trefi 37.5 9*trefi 37.5 9*trefi ns ddr3 (l) 2 gb sdram nt5c b( c ) 256 m8 f n / nt5cb(c) 128 m16 f p version 1. 6 3 nanya technology cooperation ? 0 4 / 201 4 all rights reserved. description s the 2gb double - data - rate - 3 (ddr3 (l) ) is double data rate architecture to achieve high - speed operation . it is internally configured as an eight bank dram s . the 2gb chip is organized as 32mbit x 8 i/os x 8 banks or 16mbit x 16 i/os x 8 bank devices. these synchronous devices achiev e high speed double - data - rate transfer rates of up to 1 866 mb/sec/pin for general applications. the chip is designed to comply with all key ddr3 (l) dram key features and all of the control and address inputs are synchronized with a pair of externally suppl ied differential clocks. inputs are latched at the cross point of differential clocks (ck rising and ?? falling). all i/os are synchronized with a single ended dqs or differential dqs pair in a source synchronous fashion. these devices operate with a sing le 1.5v 0.075v or 1.35v - 0.067v/+0.1v power supply and are available in bga packages. ddr3 (l) 2 gb sdram nt5c b( c ) 256 m8 f n / nt5cb(c) 128 m16 f p version 1. 6 4 nanya technology cooperation ? 0 4 / 201 4 all rights reserved. ordering information organization part number package speed 3 clock (m hz ) data rate (mb/s) cl - trcd - trp ddr3 c ommercial grade 256m x 8 nt5cb256m8 f n - d i 78 - ball 800 d dr3 - 1600 11 - 11 - 11 nt5cb256m8fn - ej 933 ddr3 - 1866 12 - 12 - 12 nt5cb256m8fn - ek 1 933 ddr3 - 1866 13 - 13 - 13 nt5cb256m8fn - fl 1066 ddr3 - 2133 14 - 14 - 14 128m x 16 nt5cb128m16fp - di 96 - ball 800 ddr3 - 1600 11 - 11 - 11 nt5cb128m16fp - ej 933 ddr3 - 1866 12 - 12 - 12 nt5cb1 28m16fp - ek 1 933 ddr3 - 1866 13 - 13 - 13 nt5cb128m16fp - fl 1066 ddr3 - 2133 14 - 14 - 14 ddr3l c ommercial grade organization part number package speed 3 clock (m hz ) data rate (mb/s) cl - trcd - trp 256m x 8 nt5c c 256m8 f n - di 78 - ball 800 ddr3l - 1600 4 11 - 11 - 11 nt5c c 256 m8 f n - dib 800 ddr3l rs - 1600 11 - 11 - 11 nt5cc256m8fn - ek 933 ddr3 l - 1866 4 13 - 13 - 13 128 m x 16 nt5c c128 m 16fp - di 96 - ball 800 ddr3l - 1600 4 11 - 11 - 11 nt5c c128 m 16fp - dib 800 ddr3l rs - 1600 11 - 11 - 11 nt5cc128m16fp - ek 933 ddr3 l - 1866 4 13 - 13 - 13 ddr3 industrial grade organization part number package speed 3 clock (m hz ) data rate (mb/s) cl - trcd - trp 256m x 8 nt5c c 256m8 f n - dii 78 - ball 800 ddr3l - 1600 4 11 - 11 - 11 nt5cb256m8 f n - dii 800 ddr3 - 1600 11 - 11 - 11 128 m x 16 nt5c c 128m16 f p - dii 96 - ball 800 ddr3l - 1600 4 11 - 11 - 11 nt5cb1 28m16 f p - dii 800 ddr3 - 1600 11 - 11 - 11 ddr3(l) automotive grade 2 128 m x 16 nt5cb128m16 f p - dia 96 - ball 800 ddr3 - 1600 11 - 11 - 11 nt5cb128m16fp - dih 800 ddr3 - 1600 11 - 11 - 11 nt5cc128m16fp - dia 800 ddr3l - 1600 4 11 - 11 - 11 nt5cc128m16fp - dih 800 ddr3l - 1600 4 11 - 11 - 1 1 note 1 m ains tream product . note 2 please confirm with ntc for the available schedule. note 3 t he timing specification of high speed bin is backward compatible with low speed bin . note 4 1.35v ddr3l are backward compatible to 1.5v ddr3 parts. 1.35v ddr3l - rs parts are excep tional and unallowable to be compatible to 1.35v ddr3l and 1.5v ddr3 parts. ddr3 (l) 2 gb sdram nt5c b( c ) 256 m8 f n / nt5cb(c) 128 m16 f p version 1. 6 5 nanya technology cooperation ? 0 4 / 201 4 all rights reserved. n t n a n y a t e c h n o l o g y 5 c p r o d u c t f a m i l y 5 s = s d r a m 5 d = d d r s d r a m 5 t = d d r 2 s d r a m 5 c = d d r 3 s d r a m b 2 5 6 m 8 f n d i n a n y a c o m p o n e n t p a r t n u m b e r i n g g u i d e o r g a n i z a t i o n ( d e p t h , w i d t h ) 4 m 1 6 = 8 m 8 = 6 4 m b 8 m 1 6 = 1 6 m 8 = 1 2 8 m b 1 6 m 1 6 = 3 2 m 8 = 6 4 m 4 = 2 5 6 m b 3 2 m 1 6 = 6 4 m 8 = 1 2 8 m 4 = 5 1 2 m b 6 4 m 1 6 = 1 2 8 m 8 = 2 5 6 m 4 = 1 g b 1 2 8 m 1 6 = 2 5 6 m 8 = 5 1 2 m 4 = 2 g b 2 5 6 m 1 6 = 5 1 2 m 8 = 1 0 2 4 m 4 = 4 g b n o t e : m = m o n o d e v i c e v e r s i o n a = 1 s t v e r s i o n b = 2 n d v e r s i o n c = 3 r d v e r s i o n d = 4 t h v e r s i o n e = 5 t h v e r s i o n f = 6 t h v e r s i o n g = 7 t h v e r s i o n h = 8 t h v e r s i o n s p e e d s d r a m 7 5 b = p c - 1 3 3 3 - 3 - 3 6 k = p c - 1 6 6 3 - 3 - 3 d d r s d r a m 6 k = d d r - 3 3 3 2 . 5 - 3 - 3 5 t = d d r - 4 0 0 3 - 3 - 3 d d r 2 s d r a m 5 a = d d r 2 - 4 0 0 3 - 3 - 3 3 7 b = d d r 2 - 5 3 3 4 - 4 - 4 3 c = d d r 2 - 6 6 7 5 - 5 - 5 2 5 c / a c = d d r 2 - 8 0 0 5 - 5 - 5 2 5 d / a d = d d r 2 - 8 0 0 6 - 6 - 6 b e = d d r 2 - 1 0 6 6 7 - 7 - 7 b d = d d r 2 - 1 0 6 6 6 - 6 - 6 d d r 3 s d r a m a c = d d r 3 - 8 0 0 5 - 5 - 5 a d = d d r 3 - 8 0 0 6 - 6 - 6 b e = d d r 3 - 1 0 6 6 7 - 7 - 7 b f = d d r 3 - 1 0 6 6 8 - 8 - 8 c f = d d r 3 - 1 3 3 3 8 - 8 - 8 c g = d d r 3 - 1 3 3 3 9 - 9 - 9 d h = d d r 3 - 1 6 0 0 1 0 - 1 0 - 1 0 d i = d d r 3 - 1 6 0 0 1 1 - 1 1 - 1 1 e j = d d r 3 - 1 8 6 6 1 2 - 1 2 - 1 2 e k = d d r 3 - 1 8 6 6 1 3 - 1 3 - 1 3 s p e c i a l t y p e o p t i o n p a c k a g e c o d e r o h s + h a l o g e n f r e e s = t s o p ( i i ) n = 7 8 - b a l l b g a p = 9 6 - b a l l b g a e = 6 0 - b a l l b g a j = 6 8 - b a l l b g a m = 9 2 - b a l l b g a u = 7 1 - b a l l b g a y = 6 3 - b a l l b g a g = d d r 1 b g a / d d r 2 8 4 - b a l l b g a 8 = 1 3 6 - b a l l b g a f k = d d r 3 - 2 1 3 3 1 3 - 1 3 - 1 3 i n t e r f a c e & p o w e r ( v d d & v d d q ) v = l v t t l ( 3 . 3 v , 3 . 3 v ) e = l v t t l ( 2 . 5 v , 2 . 5 v ) s = ( 2 . 5 v , 2 . 5 v ) m = l v t t l ( 1 . 8 v , 1 . 8 v ) u = s s t l _ 1 8 ( 1 . 8 v , 1 . 8 v ) b = s s t l _ 1 5 ( 1 . 5 v , 1 . 5 v ) a = s s t l _ 1 8 ( 2 . 0 v , 2 . 0 v ) c = s s t l _ 1 3 5 ( 1 . 3 5 v , 1 . 3 5 v ) s s t l _ 2 f = s s t l 1 2 5 ( 1 . 2 5 v , . 1 . 2 5 v _ ) d g = d d r 3 - 1 6 0 0 9 - 9 - 9 f l = d d r 3 - 2 1 3 3 1 4 - 1 4 - 1 4 i = i n d u s t r i a l g r a d e b = r e d u c e d s t a n d b y h = a u t o m o t i v e g r a d e 2 a = a u t o m o t i v e g r a d e 3 ddr3 (l) 2 gb sdram nt5c b( c ) 256 m8 f n / nt5cb(c) 128 m16 f p version 1. 6 6 nanya technology cooperation ? 0 4 / 201 4 all rights reserved. ball configuration C 78 b all bga package ( x 8) ddr3 (l) 2 gb sdram nt5c b( c ) 256 m8 f n / nt5cb(c) 128 m16 f p version 1. 6 7 nanya technology cooperation ? 0 4 / 201 4 all rights reserved. ball configuration C 96 b all bga package (x16) ddr3 (l) 2 gb sdram nt5c b( c ) 256 m8 f n / nt5cb(c) 128 m16 f p version 1. 6 8 nanya technology cooperation ? 0 4 / 201 4 all rights reserved. ball description s symbol type function ?? input clock: ck and ?? are differential clock inputs. all address and control input signals are sampled on the crossing of the positive edge of ck and negative edge of ?? . cke input clock enable: cke high activates, and cke low deactivates, intern al clock signals and device input buffers and output drivers. taking cke low provides precharge power - down and self - refresh operation (all banks idle), or active power - down (row active in any bank). cke is synchronous for power down entry and exit and for self - refresh entry. cke is asynchronous for self - refresh exit. after vref has become stable during the power on and initialization sequence, it must be maintained for proper operation of the cke receiver. for proper self - refresh entry and exit, vref must m aintain to this input. cke must be maintained high throughout read and write accesses. input buffers, excluding ck, ?? , odt and cke are disabled during power down. input buffers, excluding cke, are disabled during self - refresh. ?? input chip select: all c ommands are masked when ?? is registered high. ?? provides for external rank selection on systems with multiple memory ranks. ?? is considered part of the command code. ra? , ?a? , we input command inputs: ra? , ?a? and we (along with ?? ) define the command being entered. f or x 8 , dm f or x 16 , dmu, dml input input data mask: dm is an input mask signal for write data. input data is masked when dm is sampled high coincident with that input data during a write access. dm is sampled on both edges of dqs. for x8 de vice, the function of dm or tdqs/ t??? is enabled by mode register a11 setting in mr1 . ba0 - ba2 input bank address inputs: ba0, ba1, and ba2 define to which bank an active, read, write or precharge command is being applied. bank address also determines which mode register is to be access ed during a mrs cycle. a10 / ap input auto - p recharge : a10 is sampled during read/write commands to determine whether autoprecharge should be performed to the accessed bank after the read/write operation. (high: autoprecharge; low: no autoprecharge). a10 is sampled during a precharge command to determine whether the precharge applies to one bank (a10 low) or all banks (a10 high). if only one bank is to be precharged, the bank is selected by bank addresses. f or x 8 , a0 C a1 4 f or x 16 , a0 C a1 3 input address inputs: provide the row address for activate commands and the column address for read/write commands to select one location out of the memory array in the respective bank. (a10/ap and a12/ ?? have additional function as below. ) the address inputs also provi de the op - code during mode register set commands. a12 / ?? input burst chop: a12/ ??? is sampled during read and write commands to determine if burst chop (on the fly) will be performed. (high - no burst chop; low - burst chopped). odt input on die terminati on: odt (registered high) enables termination resistance internal to the ddr3 sdram. when enabled, odt is applied to each dq, dqs, ???? and dm/tdqs, nu/ t??? (when tdqs is enabled via mode register a11=1 in mr1) signal for x8 configurations. the odt pin will be ignored if mode - registers, mr1and mr2, are programmed to disable rtt. ddr3 (l) 2 gb sdram nt5c b( c ) 256 m8 f n / nt5cb(c) 128 m16 f p version 1. 6 9 nanya technology cooperation ? 0 4 / 201 4 all rights reserved. symbol type function re?et input active low asynchronous reset: reset is active when re?et is low, and inactive when re?et is high. re?et must be high during normal operation. re?e t is a cmos rail to rail signal with dc high and low at 80% and 20% of vdd, i.e. 1.20v for dc high and 0.30v . dq input/output data inputs/output: bi - directional data bus. dq0 is the prime dq in a low byte lane of x4/x8 /x16 configuration and dq 8 is the pri me dq in a high byte lane of x 16 configuration for write leveling . f or x8 , dqs, ( ??? ) f or x16, dqsl,( ???l ), dqsu,( ???u ) input/output data strobe: output with read data, input with write data. edge aligned with read data, centered with write data. the dat a strobes dqs, dqsl, dqsu are paired with differential signals ??? , ???l , ???u , respectively, to provide differential pair signaling to the system during both reads and writes. ddr3 sdram supports differential data strobe only and does not support single - e nded. f or x 8 , tdqs, ( t??? ) output termination data strobe: tdqs/ t??? is applicable for x8 drams only. when enabled via mode register a11=1 in mr1, dram will enable the same termination resistance function on tdqs/ t??? that is applied to dqs/ ??? . when dis abled via mode register a11=0 in mr1, dm/ t??? will provide the data mask function and t??? is not used. x16 drams must disable the tdqs function via mode register a11=0 in mr1. nc - no connect: no internal electrical connection is present. v ddq supply d q power supply: 1.35v - 0.067v/+0.1v or 1.5v 0.075 v v dd supply power supply: 1.35v - 0.067v/+0.1v or 1.5v 0.075v v ssq supply dq ground v ss supply ground v refca supply reference voltage for ca v refdq supply reference voltage for dq zq supply refere nce pin for zq calibration. note s : 1. input only pins (ba0 - ba2, a0 - a1 4 , ra? , ?a? , we , ?? , cke, odt, and re?et ) do not supply termination. 2. the signal may show up in a different symbol but it indicate s the same thing . e.g., /ck = ck# = ?? = ckb , /dqs = dqs# = ??? = dqsb , /cs = cs# = ?? = csb. ddr3 (l) 2 gb sdram nt5c b( c ) 256 m8 f n / nt5cb(c) 128 m16 f p version 1. 6 10 nanya technology cooperation ? 0 4 / 201 4 all rights reserved. simplified state diagram state diagram command definitions abbr . function abbr . function abbr . function act active read rd, rds4, rds8 pde enter power - down pre precharge read a rda, rdas4, rdas8 pdx exit power - down prea precharge all write wr, wrs4, wrs8 s re self - refresh entry mrs mode register set write a wra, wras4, wras8 srx self - refresh exit ref refresh reset start reset procedure mpr multi - purpose register zqcl zq calibration long zqcs zq calibration short - - p o w e r o n p o w e r a p p l i e d r e s e t p r o c e d u r e f r o m a n y s t a t e r e s e t i n i t i a l i z a t i o n z q c a l i b r a t i o n i d l e m r s , m p r , w r i t e l e v e l i z i n g s e l f r e f r e s h r e f r e s h i n g s r e s r x r e f a c t i v a t i n g a c t p r e c h a r g e p o w e r d o w n p d e p d x a c t i v e p o w e r d o w n b a n k a c t i v e w r i t i n g w r i t i n g p r e c h a r g i n g r e a d i n g w r i t e w r i t e a r e a d a w r i t e r e a d w r i t e a r e a d a w r i t e r e a d p r e , p r e a p r e , p r e a w r i t e a r e a d a p r e , p r e a p d x p d e r e a d i n g r e a d a u t o m a t i c s e q u e n c e c o m m a n d s e q u e n c e m r s z q c l z q c l z q c s ddr3 (l) 2 gb sdram nt5c b( c ) 256 m8 f n / nt5cb(c) 128 m16 f p version 1. 6 11 nanya technology cooperation ? 0 4 / 201 4 all rights reserved. basic functionality the ddr3(l) sdram is a high - speed dynamic random access memory internally configured as an eight - bank dram. the ddr3(l) sdram uses an 8n prefetch architecture to achieve high speed operation. the 8n prefetch architecture is combined with an interface designed to transfer t wo data words per clock cycle at the i/o pins. a single read or write operation for the ddr3(l) sdram consists of a single 8n - bit wide, four clock data transfer at the internal dram core and two corresponding n - bit wide, one - half clock cycle data transfers at the i/o pins. read and write operation to the ddr3(l) sdram are burst oriented, start at a selected location, and continue for a burst length of eight or a chopped burst of four in a programmed sequence. operation begins with the registration of an a ctive command, which is then followed by a read or write command. the address bits registered coincident with the active command are used to select the bank and row to be activated (ba0 - ba2 select the bank; a0 - a1 4 select the row). th e address bit registere d coinci dent with the read or write command are used to select the starting column location for the burst operation, determine if the auto precharge command is to be issued (via a10), and select bc4 or b l 8 mode on the fly (via a12) if enabled in the mode register. prior to normal operation, the ddr3(l) sdram must be powered up and initialized in a predefined manner. the following sections provide detailed information covering device reset and initialization, register definition, command descriptions and d evice oper ation. reset and initialization procedure power - up initialization sequence the following sequence is required for power up and initialization 1. apply power ( re?et is recommended to be maintained below 0.2 x vdd, all other inputs may be undefin ed). re?et needs to be maintained for minimum 200 s with stable power. cke is pulled low anytime before re?et? being de - asserted (min. time 10ns). the power voltage ramp time between 300mv to vdd min must be no greater than 200ms; and during the ramp, vdd> vddq and (vdd - vddq) <0.3 volts. - vdd and vddq are driven from a single power converter output, and - the voltage levels on all pins other than vdd, vddq, vss, vssq must be less than or equal to vddq and vdd on one side and must be larger than or equal to vssq and vss on the other side. in addition, vtt is limited to 0.95v max once power ramp is finished, and - v ref tracks vddq/2. or - apply vdd without any slope reversal before or at the same time as vddq. - apply vddq without any slope reversal before or at the same time as vtt & v ref . - the voltage levels on all pins other than vdd, vddq, vss, vssq must be less than or equal to vddq and vdd on one side and must be larger than or equal to vssq and vss on the other side. 2. after re?et? is de - asserted, wait for another 500us until cke become active. during this time, the dram will start inter nal state initialization; this will be done independently of external clocks. 3. clock (ck, ?? ) need to be started and stabilized for at least 10ns or 5tck (which is lar ger) before cke goes active. since cke is a synchronous signal, the corresponding set up time to clock (t is ) must be meeting. also a nop or ddr3 (l) 2 gb sdram nt5c b( c ) 256 m8 f n / nt5cb(c) 128 m16 f p version 1. 6 12 nanya technology cooperation ? 0 4 / 201 4 all rights reserved. deselect command must be registered (with t is set up time to clock) before cke goes active. once the cke registered high after reset, cke needs to be continuously registered high until the initialization sequence is finished, including expi ration of t dllk and t zqinit . 4. the ddr3(l) dram will keep its on - die termination in high impedance state as long as re?et? is asserted. further, the dram keeps its on - die termination in high impedance state after re?et de - assertion until cke is registered high. the odt input signal may be in undefined state until tis before cke is registered high. when cke is registered high, the odt input signal may be statically held at either low or high. if rtt_nom is to be enabled in mr1, the odt input signal must be statically held low. in all cases, the odt input signal remains static until the power up initialization sequence is f inished, including the expiration of tdllk and tzqinit. 5. after cke being registered high, wait minimum of reset cke exit time, txpr, before issuing the first mrs command to load mode register. [txpr=max (txs, 5tck)] 6. issue mrs command to load mr2 with all application settings. (to issue mrs command for mr2, provide low to ba0 and ba2, high to ba1) 7. issue mrs command to load mr3 with all application settings. (to issue mrs command for mr3, provide low to ba2, high to ba0 and ba1) 8. issue mrs c ommand to load mr1 with all application settings and dll enabled. (to issue dll enable command, pro vide low to a0, high to ba0 and low to ba1 and ba2) 9. issue mrs command to load mr0 with all application settings and dll reset. (to issue dll re set command, provide high to a8 and low to ba0 - ba2) 10. issue zqcl command to starting zq calibration. 11. wait for both t dllk and t zqinit completed. 12. the ddr3 (l) sdram is now ready for normal operation. ddr3 (l) 2 gb sdram nt5c b( c ) 256 m8 f n / nt5cb(c) 128 m16 f p version 1. 6 13 nanya technology cooperation ? 0 4 / 201 4 all rights reserved. reset and initialization sequence at power - on ramping (contd) reset procedure at stable power (contd) the following sequence is required for reset at no power interruption initialization. 1. asserted reset below 0.2*vdd anytime when reset is needed (all other inputs may be undefined). reset needs to be maintained for minimum 100ns. cke is pulled low before reset being de - asserted (min. time 10ns). 2. follow power - up initialization sequence step 2 to 11. 3. the reset sequence is now completed. ddr3 (l) sdram is rea dy for normal operation. reset procedure at power stable condition c k c k t c k s r x r e s e t c k e t i s o d t c o m m a n d b a 0 - b a 2 t = 2 0 0 u s t = 5 0 0 u s t x p r t m r d t m r d t m r d t m o d t z q i n i t . d o n o t c a r e t i m e b r e a k 1 0 n s m r s m r s m r s m r s z q c l m r 2 m r 3 m r 1 m r 0 v d d , v d d q * f r o m t i m e p o i n t t d u n t i l t k . n o p o r d e s c o m m a n d s m u s t b e a p p l i e d b e t w e e n m r s a n d z q c a l c o m m n a d s . t e t k n o p * n o p * v a l i d v a l i d s t a t i c l o w i n c a s e r t t _ n o m i s e n a b l e d a t t i m e t g , o t h e r w i s e s t a t i c h i g h o r l o w t d t c t a t b t f t g t h t i t j t d l l k v a l i d v a l i d c k c k t c k s r x r e s e t c k e t i s o d t c o m m a n d b a 0 - b a 2 t = 1 0 0 n s t = 5 0 0 u s t x p r t m r d t m r d t m r d t m o d t z q i n i t . d o n o t c a r e t i m e b r e a k 1 0 n s m r s m r s m r s m r s z q c l m r 2 m r 3 m r 1 m r 0 v d d , v d d q * f r o m t i m e p o i n t t d u n t i l t k . n o p o r d e s c o m m a n d s m u s t b e a p p l i e d b e t w e e n m r s a n d z q c a l c o m m n a d s . t e t k n o p * n o p * v a l i d v a l i d s t a t i c l o w i n c a s e r t t _ n o m i s e n a b l e d a t t i m e t g , o t h e r w i s e s t a t i c h i g h o r l o w t d t c t a t b t f t g t h t i t j t d l l k v a l i d v a l i d ddr3 (l) 2 gb sdram nt5c b( c ) 256 m8 f n / nt5cb(c) 128 m16 f p version 1. 6 14 nanya technology cooperation ? 0 4 / 201 4 all rights reserved. vddq/vddq voltage switch between ddr3l and ddr3 ddr3 (l) 2 gb sdram nt5c b( c ) 256 m8 f n / nt5cb(c) 128 m16 f p version 1. 6 15 nanya technology cooperation ? 0 4 / 201 4 all rights reserved. register definition programming the mode registers for application flexibility, various f unctions, features, and modes are programmable in four mode registers, provided by the ddr3 (l) sdram, as user defined variables and they must be programmed via a mode register set (mrs) command. as the default values of the mode registers ( ?r ) are not def ined, contents of mode registers must be fully initialized and/or re - initialized, i.e. written, after power up and/or reset for proper operation. also the contents of the mode registers can be altered by re - executing the mrs command during normal operation . when programming the mode registers, even if the user chooses to modify only a sub - set of the mrs fields, all address fields within the accessed mode register must be redefined when the mrs command is issued. mrs command and dll reset do not affect array content s , which mean these commands can be executed any time after power - up without affecting the array contents . the mode register set command cycle time, t mrd is required to complete the write operation to the mode register and is the minimum time requi red between two mrs commands shown as below. t mrd timing the mrs command to non - mrs command delay, t mod , is require for the dram to update the features except dll reset, and is the minimum time required from an mrs command to a non - mrs command excluding nop and des shown as the following figure. c k c k c k e d o n o t c a r e t i m e b r e a k m r s n o p n o p n o p n o p c m d v a l v a l a d d r t m r d m r s ddr3 (l) 2 gb sdram nt5c b( c ) 256 m8 f n / nt5cb(c) 128 m16 f p version 1. 6 16 nanya technology cooperation ? 0 4 / 201 4 all rights reserved. t mod timing programming the mode registers (contd) the mode register contents can be changed using the same command and timing requirements during normal operation as long as the dram is in idle state, i.e. all banks are in the precharged state with trp satisfied, all data bursts are complet ed and cke is high prior to writing into the mode register. the mode registers are divided into various fields depend ing on the functionality and/or modes. mode register mr0 the mode - register mr0 stores data for controlling various operating modes of ddr3 (l) sdram. it controls burst length, read burst type, cas latency, test mode, dll reset, wr, and dll control for pre charge power - down, which include various vendor specific options to make ddr3(l) sdram useful for various applications. the mode register is written by asserting low on ?? , ra? , ?a? , we , ba0, ba1, and ba2, while controlling the states of address pins according to the following figure. c k c k c k e m r s n o p n o p n o p n o p c m d a d d r t m o d n o n m r s v a l o l d s e t t i n g u p d a t i n g s e t t i n g n e w s e t t i n g v a l v a l ddr3 (l) 2 gb sdram nt5c b( c ) 256 m8 f n / nt5cb(c) 128 m16 f p version 1. 6 17 nanya technology cooperation ? 0 4 / 201 4 all rights reserved. mr0 definition *1: ba2 and a13~a15 are rfu and must be programmed to 0 during mrs. *2: wr (write recovery for autoprecharge)min in clock cycles is calculated by dividing twr(in ns) by tck(in ns) and rounding up to the next integer: wrmin[cycles] = roundup(twr[ns] / tck[ns]). the wr value in the mode register must be programmed to be equal or larger than wrmin. the programmed wr value is used with trp to determine tdal. *3: the table only shows the encodings for a given cas latency. for actual supported cas latency, please refer to speedbin ta ble s for each frequency *4: the table only shows the encodings for write recovery. for actual write recovery timing, please refer to ac timingtable. ba2 ba1 ba0 a15-a13 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 0 0 ppd dll tm rbt cl a12 a8 a3 0 0 0 1 1 1 ba1 ba0 mr select a7 0 0 mr0 0 0 1 mr1 1 a1 a0 1 0 mr2 0 0 1 1 mr3 0 1 1 0 a11 a10 a9 1 1 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 a6 a5 a4 a2 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0 0 1 0 1 0 1 1 0 0 1 1 1 0 0 0 0 1 0 0 1 1 0 1 0 1 0 1 1 1 1 0 0 1 1 0 1 1 1 1 0 1 1 1 1 1 wr cas latency bl mr select slow exit(dll off) ppd fast exit(dll on) wr dll reset no yes mode normal test reserved read burst type nibble sequential interleave 5 6 7 8 12 14 16 10 11 10 12 reserved reserved bc4(fixed) bl 8(fixed) bc4 or 8 (on the fly) reserved cas latency 5 reserved reserved 6 7 8 9 13 14 reserved ddr3 (l) 2 gb sdram nt5c b( c ) 256 m8 f n / nt5cb(c) 128 m16 f p version 1. 6 18 nanya technology cooperation ? 0 4 / 201 4 all rights reserved. burst length, type, and order accesses within a given burst may be programmed to sequential or interleave d order. the burst type is selected via bit a3 as shown in the mr0 definition as above figure. the ordering of access within a burst is determined by the burst length, burst type, and the starting column address. the burst length is defined by bits a0 - a1. burst lengths options include fix bc4, fixed bl8, and on the fly which allow bc4 or bl8 to be selected coincident with the registration of a read or write command via a12/ ?? . burst type and burst order burst length read write starting column address (a2,a1,a0) burst type : sequential (decimal) a3 = 0 burst type : interleaved (decimal) a3 = 1 note 4 chop read 0,0,0 0,1,2,3,t,t,t,t 0,1,2,3,t,t,t,t 1,2,3 0,0,1 1,2,3,0,t ,t,t,t 1,0,3,2,t,t,t,t 0,1,0 2,3,0,1,t,t,t,t 2,3,0,1,t,t,t,t 0,1,1 3,0,1,2,t,t,t,t 3,2,1,0,t,t,t,t 1,0,0 4,5,6,7,t,t,t,t 4,5,6,7,t,t,t,t 1,0,1 5,6,7,4,t,t,t,t 5,4,7,6,t,t,t,t 1,1,0 6,7,4,5,t,t,t,t 6,7,4,5,t,t,t,t 1,1,1 7,4,5,6,t,t,t ,t 7,6,5,4,t,t,t,t write 0,v,v 0,1,2,3,x,x,x,x 0,1,2,3,x,x,x,x 1,2,4,5 1,v,v 4,5,6,7,x,x,x,x 4,5,6,7,x,x,x,x 8 read 0,0,0 0,1,2,3,4,5,6,7 0,1,2,3,4,5,6,7 2 0,0,1 1,2,3,0,5,6,7,4 1,0,3,2,5,4,7,6 0,1,0 2,3,0,1,6,7,4,5 2,3,0,1,6,7,4,5 0,1,1 3,0,1,2,7,4,5,6 3,2,1,0,7,6,5,4 1,0,0 4,5,6,7,0,1,2,3 4,5,6,7,0,1,2,3 1,0,1 5,6,7,4,1,2,3,0 5,4,7,6,1,0,3,2 1,1,0 6,7,4,5,2,3,0,1 6,7,4,5,2,3,0,1 1,1,1 7,4,5,6,3,0,1,2 7,6,5,4,3,2,1,0 write v,v,v 0,1,2,3,4,5,6,7 0,1,2,3,4,5,6,7 2,4 not e: 1. in case of burst length being fixed to 4 by mr0 setting, the internal write operation starts two clock cycles earlier than th e bl8 mode. this means that the starting point for twr and twtr will be pulled in by two clocks. in case of burst length bei ng selected on - the - fly via a12/ ?? , the internal write operation starts at the same point in time like a burst of 8 write operation. this means that during on - the - fly control, the starting point for twr and twtr will not be pulled in by two clocks. 2. 0~7 b it number is value of ca [2:0] that causes this bit to be the first read during a burst. 3. t: output driver for data and strobes are in high impedance. 4. v: a valid logic level (0 or 1), but respective buffer input ignores level on input pins. 5. x: do n ot care. ddr3 (l) 2 gb sdram nt5c b( c ) 256 m8 f n / nt5cb(c) 128 m16 f p version 1. 6 19 nanya technology cooperation ? 0 4 / 201 4 all rights reserved. cas latency the cas latency is defined by mr0 (bit a 2, a4 ~a 6 ) as shown in the mr0 definition figure. cas latency is the delay, in clock cycles, between the internal read command and the availability of the first bit of output data. ddr3(l) sdram does not support any half clock latencies. the overall read latency (rl) is defined as additive latency (al) + cas latency (cl); rl = al + cl. test mode the normal operating mode is selected by mr0 (bit7=0) and all other bits set to the desired values sho wn in the mr0 definition figure. programming bit a7 to a 1 places the ddr3(l) sdram into a test mode that is only used by the dram manufacturer and should not be used. no operations or functionality is guaranteed if a7=1. dll reset the dll reset bit is s elf - clearing, meaning it returns back to the value of 0 after the dll reset function has been issued. once the dll is enabled, a subsequent dll reset should be applied. anytime the dll reset function is used, tdllk must be met before any functions that r equire the dll can be used (i.e. read commands or odt synchronous operations.) write recovery the programmed wr value mr0(bits a9, a10, and a11) is used for the auto precharge feature along with trp to determine tdal wr (write recovery for auto - precharge)m in in clock cycles is calculated by dividing twr(ns) by tck(ns) and rounding up to the next integer: wrmin[cycles] = roundup(twr[ns]/tck[ns]). the wr must be programmed to be equal or larger than twr (min). precharge pd dll mr0 (bit a12) is used to select the dll usage during precharge power - down mode. when mr0 (a12=0), or slow - exit, the dll is frozen after entering precharge power - down (for potential power savings) and upon exit requires txpdll to be met prior to the next valid command. when mr0 (a12=1), or fast - exit, the dll is maintained after entering precharge power - down and upon exiting power - down requires txp to be met prior to the next valid command. ddr3 (l) 2 gb sdram nt5c b( c ) 256 m8 f n / nt5cb(c) 128 m16 f p version 1. 6 20 nanya technology cooperation ? 0 4 / 201 4 all rights reserved. mode register mr1 the mode register mr1 stores the data for enabling or disabling the dll, outpu t strength, rtt_nom impedance, additive latency, write leveling enable and qoff. the mode register 1 is written by asserting low on ?? , ra? , ?a? , we high on ba0 and low on ba1 and ba2, while controlling the states of address pins according to the following figure. mr1 definition * 1 : ba2 and a8, a10, and a13 ~ a15 are rfu and must be programmed to 0 during mrs. *2: outputs disabled - dqs, dqss, ??? s. * 3 : rzq = 240 * 4 : in write leveling mode (mr1[bit7] = 1) with mr1[bit12]=1, all rtt_nom settings are allowed; in write leveling mode (mr1[bit7] = 1) with mr1[bit12]=0, only rtt_nom settings of rzq/2, rzq/4 and rzq/6 are allowed. * 5 : if rtt_nom is used during writes, only the values rzq/2, rzq/4 and rzq/6 are allowed. ba2 ba1 ba0 a15-a13 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 0 0 qoff tdqs 0 rtt_nom 0 level rtt_nom d.i.c rtt_nom d.i.c dll a11 tdqs a9 a6 a2 a4 a3 0 disabled 0 0 0 0 0 1 enabled 0 0 1 0 1 0 1 0 1 0 ba1 ba0 mr select 0 1 1 1 1 0 0 mr0 1 0 0 0 1 mr1 1 0 1 a0 1 0 mr2 1 1 0 0 1 1 mr3 1 1 1 1 a7 a5 a1 0 0 0 1 0 1 1 0 1 1 a12 0 1 output buffer disabled rzq/12 rzq/8 reserved reserved al disabled cl-1 cl-2 reserved al dll enable enable disable rzq/6 reserved qoff output buffer enabled output driver impedance rzq/7 reserved write leveling enable disabled rzq/4 disabled enabled mr select rtt_nom rzq/2 rzq/6 ddr3 (l) 2 gb sdram nt5c b( c ) 256 m8 f n / nt5cb(c) 128 m16 f p version 1. 6 21 nanya technology cooperation ? 0 4 / 201 4 all rights reserved. dll enable/disable the dll must be enabled for normal operation. dll enable is required during p ower up initialization, and upon returning to normal operation after having the dll disabled. during normal operation (dll - on) with mr1 (a0=0), the dll is automatically disabled when entering self - refresh operation and is automatically re - enable upon exit of self - refresh operation. any time the dll is enabled and subsequently reset, tdllk clock cycles must occur before a read or synchronous odt command can be issued to allow time for the internal clock to be synchronized with the external clock. failing to wait for synchronization to occur may result in a violation of the tdqsck, taon, or taof parameters. during tdllk, cke must continuously be registered high. ddr3(l) sdram does not require dll for any write operation, expect when rtt_wr is enabled and the d ll is required for proper odt operation. for more detailed information on dll disable operation in dll - off mode. the direct odt feature is not supported during dll - off mode. the on - die termination resistors must be disabled by continu - ously registering the odt pin low and/or by programming the rtt_nom bits mr1{a9,a6,a2} to {0,0,0} via a mode register set command during dll - off mode. the dynamic odt feature is not supported at dll - off mode. user must use mrs command to set rtt_wr, mr2 {a10, a9} = {0, 0}, to disable dynamic odt externally. output driver impedance control the output driver impedance of the ddr3(l) sdram device is selected by mr1 (bit a1 and a5) as shown in mr1 definition figure. odt rtt values ddr3(l) sdram is capable of providing two differe nt termination values (rtt_nom and rtt_wr). the nominal termination value rtt_nom is programmable in mr1. a separate value (rtt_wr) may be programmable in mr2 to enable a unique rtt value when odt is enabled during writes. the rtt_wr value can be applied d uring writes even when rtt_nom is disabled. ddr3 (l) 2 gb sdram nt5c b( c ) 256 m8 f n / nt5cb(c) 128 m16 f p version 1. 6 22 nanya technology cooperation ? 0 4 / 201 4 all rights reserved. additive latency (al) additive latency (al) operation is supported to make command and data bus efficient for sustainable bandwidth in ddr3(l) sdram. in this operation, the ddr3(l) sdram allows a read or write command (either with or without auto - precharge) to be issued immediately after the active command. the command is held for the time of the additive latency (al) before it is issued inside the device. the read latency (rl) is controlled by the sum of the al and cas latency (cl) register settings. write latency (wl) is controlled by the sum of the al and cas write latency (cwl) register settings. a summary of the al register options are shown as the following table. additive latency (al) settings a4 a3 al 0 0 0 , (al disable) 0 1 cl - 1 1 0 cl - 2 1 1 reserved ddr3 (l) 2 gb sdram nt5c b( c ) 256 m8 f n / nt5cb(c) 128 m16 f p version 1. 6 23 nanya technology cooperation ? 0 4 / 201 4 all rights reserved. write leveling for better signal integrity, ddr3(l) memory module adopted fly by topology for the commands, addresses, control signals, and clocks. the fly by topology has benefits from reducing number of stubs and their length but in other aspect, causes flight time skew between clock and strobe at every dram on dimm. it makes difficult for the controller to maintain tdqss, tdss, and tdsh specification. therefore, the controller should support write l eveling in ddr3(l) sdram to compensate for skew. output disable the ddr3(l) sdram outputs maybe enable/disabled by mr1 (bit12) as shown in mr1 definition. when this feature is enabled (a12=1) all output pins (dqs, dqs, ??? , etc.) are disconnected from th e device removing any loading of the output drivers. this feature may be useful when measuring modules power for example. for normal operation a12 should be set to 0. tdqs , t??? tdqs (termination data strobe) is a feature of x8 ddr3(l) sdram that pr ovides additional termination resistance outputs that may be useful in some system configurations. when enabled via the mode register, the same termination resistance function is applied to be tdqs/ t??? pins that are applied to the dqs/ ??? pins. in contras t to the rdqs function of ddr2 sdram, tdqs provides the termination resistance function only. the data strobe function of rdqs is not provided by tdqs. the tdqs and dm functions share the same pin. when the tdqs function is enabled via the mode register, t he dm function is not supported. when the tdqs function is disabled, the dm function is provided and the t??? pin is not used. the tdqs function is available in x8 ddr3(l) sdram only and must be disabled via the mode register a11=0 in mr1 for x16 configurations. tdqs, t??? mr1 (a11) dm / tdqs nu / tdqs 0 (tdqs disabled) dm hi - z 1 (tdqs enab led) tdqs t??? note: 1. if tdqs is enabled, the dm function is disabled. 2. when not used, tdqs function can be disabled to save termination power. 3. tdqs function is only available for x8 dram and must be disabled for x16. ddr3 (l) 2 gb sdram nt5c b( c ) 256 m8 f n / nt5cb(c) 128 m16 f p version 1. 6 24 nanya technology cooperation ? 0 4 / 201 4 all rights reserved. mode register mr2 the mode r egister mr2 stores the data for controlling refresh related features, rtt_wr impedance, and cas write latency. the mode register 2 is written by asserting low on ?? , ra? , ?a? , we high on ba1 and low on ba0 and ba2, while controlling the states of address p ins according to the table below. mr2 definition * 1 : default state of pasr is disabed. th is is enabled by using an electrical fuse. please contact with ntc for the demand. * 2 : ba2, a5, a8, a11 ~ a15 are rfu and must be programmed to 0 during mrs. * 3 : the rtt_wr value can be applied during writes even when rtt_nom is disabled. during write leveling, dynamic odt is not available. ba2 ba1 ba0 a15-a13 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 0 0 srt asr a6 a2 a1 a0 0 0 0 0 1 0 0 1 0 1 0 0 1 1 1 0 0 a10 a9 1 0 1 0 0 1 1 0 0 1 1 1 1 1 0 1 1 a5 a4 a3 0 0 0 a7 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 ba1 ba0 1 1 1 0 0 0 1 1 0 1 1 quarter array (ba[2:0]=110, &111) 1/8th array (ba[2:0]=111) pasr full array halfarray (ba[2:0]=000,001,010, &011) quarter array (ba[2:0]=000, & 001) 1/8th array (ba[2:0] = 000) 3/4 array (ba[2:0] = 010,011,100,101,110, & 111) halfarray (ba[2:0] = 100, 101, 110, &111) mr select 0 rtt_wr cwl pasr rfu cwl 7 (1.875ns>=tck(avg)>=1.5ns) 8 (1.5ns>=tck(avg)>=1.25ns) 9 (1.25ns>=tck(avg)>=1.07ns) asr manual sr reference (srt) asr enable rtt_wr dynamic odt off rzq/4 rzq/2 reserved 6 (2.5ns>=tck(avg)>=1.875ns) srt mr select mr0 10 (1.07ns>=tck(avg)>=0.935ns) rfu 5 (tck(avg)>=2.5ns) mr1 mr2 mr3 normal operating temperature range extended operating temperature range 0 1 ddr3 (l) 2 gb sdram nt5c b( c ) 256 m8 f n / nt5cb(c) 128 m16 f p version 1. 6 25 nanya technology cooperation ? 0 4 / 201 4 all rights reserved. cas write latency (cwl) the cas write latency is defined by mr2 (bits a3 - a5) shown in mr2. cas write latency is the delay, in clock cycles, between the internal write command and the availability of the first bit of input data. ddr3(l) dram does n ot support any half clock laten cies. the overall write latency (wl) is defined as additive latency (al) + cas write latency (cwl); wl=al+cwl. auto self - refresh (asr) and self - refresh temperature (srt) d dr3(l) sdram must support self - refresh operation at all supported temperatures. applications requiring self - refresh operation in the extended temperature range must use the asr function or program the srt bit appropriately. optional in ddr3(l) sdram: users should refer to the dram supplier data sheet and/or the dimm spd to determine if ddr3(l) sdram devices support the following options or requirements referred to in this material. for more details refer to extended temperature usage. ddr3(l) sdrams must support self - refresh operation at all supported temperatures. applications requiring self - refresh operation in the extended temperature range must use the optional asr function or program the srt bit appropriately. dynamic odt (rtt_wr) ddr3(l) sdram intro duces a new feature dynamic odt. in certain application cases and to further enhance signal integrity on the data bus, it is desirable that the termination strength of the ddr3(l) sdram can be changed without issuing an mrs command. mr2 register location s a9 and a10 configure the dynamic odt settings. in write leveling mode, only rtt_nom is available. for details on dynamic odt operation, refer to dynamic odt . ddr3 (l) 2 gb sdram nt5c b( c ) 256 m8 f n / nt5cb(c) 128 m16 f p version 1. 6 26 nanya technology cooperation ? 0 4 / 201 4 all rights reserved. mode register mr3 the mode register mr3 controls multi - purpose registers. the mode register 3 is written by asserting low on ?? , ra? , ?a? , we high on ba1 and ba0, and low on ba2 while controlling the states of address pins according to the table below. mr3 definition * 1 : ba2, a3 - a15 are rfu and must be programmed to 0 during mrs. * 2 : the pre defined pattern will be used for read synchronization. * 3 : when mpr control is set for normal operation (mr3 a[2] = 0) then mr3 a[1:0] will be ignored. ba2 ba1 ba0 a15-a13 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 0 mpr a2 a1 a0 0 0 0 1 0 1 1 0 ba1 ba0 mr select 1 1 0 0 mr0 0 1 mr1 1 0 mr2 1 1 mr3 normal operation dataflow from mpr mpr loc 0 predefined pattern reserved reserved reserved mpr loc mpr mr select ddr3 (l) 2 gb sdram nt5c b( c ) 256 m8 f n / nt5cb(c) 128 m16 f p version 1. 6 27 nanya technology cooperation ? 0 4 / 201 4 all rights reserved. multi - purpose register (mpr) the multi purpose register (mpr) function is used to read out a predefined system timing calibration bit sequence. to enable the mpr, a mode register set (mrs) command must be issued to mr3 register with bit a2=1. prior to issuing the mrs command, all banks must be in the idle state (all banks precharged and trp met). once the mp r is enabled, any subsequent rd or rda commands will be redirected to the multi purpose register. when the mpr is enabled, only rd or rda commands are allowed until a subsequent mrs command is issued with the mpr disabled (mr3 bit a2=0). power down mode, s elf - refresh and any other non - rd/rda command is not allowed during mpr enable mode. the reset function is supported during mpr enable mode. the multi purpose register (mpr) function is used to read out a predefined system timing calibration bit sequence. fig. 1 : mpr block diagram to enable the mpr, a mode register set (mrs) command must be issued to mr3 register with bit a2 = 1, p rior to issuing the mrs command, all banks must be in the idle state (all banks precharged and trp met ). once the mpr is enabled, any subsequent rd or rda commands will be redirected to the multi purpose register. the resulting operation, when a rd or rda command is issued, is defined by mr3 bits a [1:0] when the mp r is enabled as shown . when the mpr is ena bled, only rd or rda commands are allowed until a subsequent mrs command is issued with the mpr disabled (mr3 bit a2 = 0). note that in mpr mode rda has the same functionality as a read command which means the auto precharge part of rda is ignored. power - d own mode, self - refresh and any other non - rd/rda command is not allowed during mpr enable mode. the reset function is supported during mpr enable mode. ddr3 (l) 2 gb sdram nt5c b( c ) 256 m8 f n / nt5cb(c) 128 m16 f p version 1. 6 28 nanya technology cooperation ? 0 4 / 201 4 all rights reserved. mpr mr3 register definition mr3 a[2] mr3 a[1:0] function mpr mpr - loc 0b don't care (0b or 1b) norma l operation, no mpr transaction. all subsequent reads will come from dram array. all subsequent write will go to dram array. 1b see mr3 table enable mpr mode, subsequent rd/rda commands defined by mr3 a[1:0]. mpr functional description ? one bit wide l ogical interface via all dq pins during read operation. ? register read on x8: ? dq [0] drives information from mpr. ? dq [7:1] either drive the same information as dq [0], or they drive 0b. ? register read on x16: ? dql [0] and dqu [0] drive information fr om mpr. ? dql [7:1] and dqu [7:1] either drive the same information as dql [0], or they drive 0b. ? addressing during for multi purpose register reads for all mpr agents: ? ba [2:0]: dont care ? a [1:0]: a [1:0] must be equal to 00b. data read burst order in nibble is fixed ? a[2]: for bl=8, a[2] must be equal to 0b, burst order is fix ed to [0,1,2,3,4,5,6,7], *) for burst chop 4 cases, the burst order is switched on nibble base a [ 2]=0b, burst order: 0,1,2,3 *) a[2]=1b, burst order: 4,5,6,7 *) ? a[9:3 ]: dont care ? a10/ap: dont care ? a12/bc: selects burst chop mode on - the - fly, if enabled within mr0. ? a11, a13... (if available): dont care ? regular interface functionality during register reads: ? support two burst ordering which are switched with a 2 and a[1:0]=00b. ? support of read burst chop (mrs and on - the - fly via a12/bc) ? all other address bits (remaining column address bits including a10, all bank address bits) will be ignored by the ddr3(l) sdram. ? regular read latencies and ac timings appl y. ? dll must be locked prior to mpr reads. note: * burst order bit 0 is assigned to lsb and burst order bit 7 is assigned to msb of the selected mpr agent. ddr3 (l) 2 gb sdram nt5c b( c ) 256 m8 f n / nt5cb(c) 128 m16 f p version 1. 6 29 nanya technology cooperation ? 0 4 / 201 4 all rights reserved. mpr mr3 register definition mr3 a[2] mr3 a[1:0] function burst length read address a[2:0] burst o rder and data pattern 1b 00b read predefined pattern for system calibration bl8 000b burst order 0,1,2,3,4,5,6,7 pre - defined data pattern [0,1,0,1,0,1,0,1] bc4 000b burst order 0,1,2,3 pre - defined data pattern [0,1,0,1] bc4 100b burst order 4,5,6 ,7 pre - defined data pattern [0,1,0,1] 1b 01b rfu bl8 000b burst order 0,1,2,3,4,5,6,7 bc4 000b burst order 0,1,2,3 bc4 100b burst order 4,5,6,7 1b 10b rfu bl8 000b burst order 0,1,2,3,4,5,6,7 bc4 000b burst order 0,1,2,3 bc4 100b burst or der 4,5,6,7 1b 11b rfu bl8 000b burst order 0,1,2,3,4,5,6,7 bc4 000b burst order 0,1,2,3 bc4 100b burst order 4,5,6,7 note: burst order bit 0 is assigned to lsb and the burst order bit 7 is assigned to msb of the selected mpr agent. ddr3 (l) 2 gb sdram nt5c b( c ) 256 m8 f n / nt5cb(c) 128 m16 f p version 1. 6 30 nanya technology cooperation ? 0 4 / 201 4 all rights reserved. ddr3(l) sd ram command description and operation command truth table function abbr . cke ?? ? ra? ? ?a? ? we ? ba0 - ba2 a13 - a1 4 a12 - ?? a10 - ap a0 - a9, a11 note s previous cycle current cycle mode register set mrs h h l l l l ba op code refresh ref h h l l l h v v v v v self refresh entry sre h l l l l h v v v v v 7,9,12 self refre sh exit srx l h h x x x x x x x x 7,8,9,12 l h h h v v v v v single bank precharge pre h h l l h l ba v v l v precharge all banks prea h h l l h l v v v h v bank activate act h h l l h h ba row address (ra) write (fixed bl8 or bc4) wr h h l h l l ba rfu v l ca write (bc4, on the fly) wrs4 h h l h l l ba rfu l l ca write (bl8, on the fly) wrs8 h h l h l l ba rfu h l ca write with auto precharge (fixed bl8 or bc4) wra h h l h l l ba rfu v h ca write with auto precharge (bc4, on the fly) w ras4 h h l h l l ba rfu l h ca write with auto precharge (bl8, on the fly) wras8 h h l h l l ba rfu h h ca read (fixed bl8 or bc4) rd h h l h l h ba rfu v l ca read (bc4, on the fly rds4 h h l h l h ba rfu l l ca read (bl8, on the fly) rds8 h h l h l h ba rfu h l ca read with auto precharge (fixed bl8 or bc4) rda h h l h l h ba rfu v h ca read with auto precharge (bc4, on the fly) rdas4 h h l h l h ba rfu l h ca read with auto precharge (bl8, on the fly) rdas8 h h l h l h ba rfu h h ca no op eration nop h h l h h h v v v v v 10 device deselected des h h h x x x x x x x x 11 power down entry pde h l l h h h v v v v v 6,12 h x x x x x x x x power down exit pdx l h l h h h v v v v v 6,12 h x x x x x x x x zq calibration long zqcl h h l h h l x x x h x zq calibration short zqcs h h l h h l x x x l x ddr3 (l) 2 gb sdram nt5c b( c ) 256 m8 f n / nt5cb(c) 128 m16 f p version 1. 6 31 nanya technology cooperation ? 0 4 / 201 4 all rights reserved. ddr3(l) sdram command description and operation command truth table (conti.) note1. all ddr3(l) sdram commands are defined by states of ?? , ra? , ?a? , we? and cke at the rising edge of the clock. the msb of ba, ra and ca are device density and configuration dependant. note2. re?et is low enable command which will be used only for asynchronous reset so must be maintained high during any funct ion. note3. bank addresses (ba) determine which bank is to be operated upon. for (e)mrs ba selects an (extended) mode register. note4. v means h or l (but a defined logic level) and x means either defined or undefined (like floating) logic level . note5. burst reads or writes cannot be terminated or interrupted and fixed/on - the - fly bl will be defined by mrs. note6. the power - down mode does not perform any refresh operation. note7. the state of odt does not affect the states described in this tab le. the odt function is not available during self refresh. note8. self refresh exit is asynchronous. note9. vref (both vrefdq and vrefca) must be maintained during self refresh operation. note10. the no operation command should be used in cases when the ddr3(l) sdram is in an idle or wait state. the purpose of the no operation command (nop) is to prevent the ddr3(l) sdram from registering any unwanted commands between operations. a no operation command will not terminate a pervious operation that is stil l executing, such as a burst read or write cycle. note11. the deselect command performs the same function as no operation command. note12. refer to the cke truth table for more detail with cke transition. ddr3 (l) 2 gb sdram nt5c b( c ) 256 m8 f n / nt5cb(c) 128 m16 f p version 1. 6 32 nanya technology cooperation ? 0 4 / 201 4 all rights reserved. cke truth table current state cke command (n) ra ? , ?a? , ?we , ?? action (n) notes previous cycle (n - 1) current cycle (n) power - down l l x maintain power - down 14,15 l h deselect or nop power - down exit 11,14 self - refresh l l x maintain self - refresh 15,16 l h deselect or nop self - refresh exit 8 ,12,16 bank(s) active h l deselect or nop active power - down entry 11,13,14 reading h l deselect or nop power - down entry 11,13,14,17 writing h l deselect or nop power - down entry 11,13,14,17 precharging h l deselect or nop power - down entry 11,13,14,1 7 refreshing h l deselect or nop precharge power - down entry 11 all banks idle h l deselect or nop precharge power - down entry 11,13,14,18 h l refresh self - refresh 9,13,18 note 1 cke (n) is the logic state of cke at clock edge n; cke (n - 1) was the st ate of cke at the previous clock edge. note 2 current state is defined as the state of the ddr3(l) sdram immediately prior to clock edge n. note 3 command (n) is the command registered at clock edge n, and action (n) is a result of command (n), odt is not included here. note 4 all states and sequences not shown are illegal or reserved unless explicitly described elsewhere in this document. note 5 the state of odt does not affect the states described in this table. the odt function is not available during se lf - refresh. note 6 cke must be registered with the same value on tckemin consecutive positive clock edges. cke must remain at the valid input level the entire time it takes to achieve the tckemin clocks of registrations. thus, after any cke transition, cke may not transition from its valid level during the time period of tis + tckemin + tih. note 7 deselect and nop are defined in the command truth table. note 8 on self - refresh exit deselect or nop commands must be issued on every clock edge occurring during the txs period. read or odt commands may be issued only after txsdll is satisfied. note 9 self - refresh modes can only be entered from the all banks idle state. note 10 must be a legal command as defined in the command truth table. note 11 valid commands f or power - down entry and exit are nop and deselect only. note 12 valid commands for self - refresh exit are nop and deselect only. note 13 self - refresh cannot be entered during read or write operations. note 14 the power - down does not perform any refresh ope rations. note 15 x means dont care(including floating around vref) in self - refresh and power - down. it also applies to address pins. note 16 vref (both vref_dq and vref_ca) must be maintained during self - refresh operation. note 17 if all banks are clos ed at the conclusion of the read, write or precharge command, then precharge power - down is entered, otherwise active power - down is entered. note 18 idle state is defined as all banks are closed (trp, tdal, etc. satisfied), no data bursts are in progress, cke is high, and all timings from previous operations are satisfied (tmrd, tmod, trfc, tzqinit, tzqoper, tzqcs, etc.) as well as all self - refresh exit and power - down exit parameters are satisfied (txs, txp, txpdll, etc). ddr3 (l) 2 gb sdram nt5c b( c ) 256 m8 f n / nt5cb(c) 128 m16 f p version 1. 6 33 nanya technology cooperation ? 0 4 / 201 4 all rights reserved. no operation (nop) command the no operation (nop) command is used to instruct the selected ddr3(l) sdram to perform a nop ( ??? low and ra? , ?a? , and we high). this prevents unwanted commands from being registered during idle or wait states. operations already in progress are not affected. deselect command the deselect function ( ??? high) prevents new commands from being executed by the ddr3(l) sdram. the ddr3(l) sdram is effectively deselected. operations already in progress are not affected. dll - o ff mode ddr3(l) dll - off mode is entered by setting mr1 bit a0 to 1; this will disable the dll for subsequent operations until a0 bi t set back to 0. the mr1 a0 bit for dll control can be switched either during initialization or later. the dll - off mode operations listed below are an optional feature for ddr3(l). the maximum clock frequency for dll - off mode is specified by the paramete r tckdll_off. there is no minimum frequency limit besides the need to satisfy the refresh interval, trefi. due to latency counter and timing restrictions, only one value of cas latency (cl) in mr0 and cas write latency (cwl) in mr2 are supported. the dll - o ff mode is only required to support setting of both cl=6 and cwl=6. dll - off mode will affect the read data clock to data strobe relationship (tdqsck) but not the data strobe to data relationship (tdqsq, tqh). special attention is needed to line up read dat a to controller time domain. comparing with dll - on mode, where tdqsck starts from the rising clock edge (al+cl) cycles after the read command, the dll - off mode tdqsck starts (al+cl - 1) cycles after the read command. another difference is that tdqsck may not be small compared to tck (it might even be larger than tck) and the difference between tdqsckmin and tdqsckmax is significantly larger than in dll - on mode. the timing relations on dll - off mode read operation have shown at the following timing diagram (cl =6, bl=8) ddr3 (l) 2 gb sdram nt5c b( c ) 256 m8 f n / nt5cb(c) 128 m16 f p version 1. 6 34 nanya technology cooperation ? 0 4 / 201 4 all rights reserved. dll - off mode read timing operation note: the tdqsck is used here for dqs, dqs , and dq to have a simplified diagram; the dll_off shift will affect both timings in the same way and the skew between all dq, dqs, and ???? signals will still be td qsq. c k c k t 0 t 1 t 2 t 3 t 4 t 5 t 6 t 7 t 8 t 9 r e a d c m d b a n k , c o l b a d d r e s s d i n b d i n b + 1 d i n b + 2 d i n b + 3 d i n b + 4 d i n b + 5 d i n b + 6 d i n b + 7 d q s d i f f _ d l l _ o n d q _ d l l _ o n d q s d i f f _ d l l _ o f f d q _ d l l _ o f f d q s d i f f _ d l l _ o f f d q _ d l l _ o f f r l = a l + c l = 6 ( c l = 6 , a l = 0 ) r l ( d l l _ o f f ) = a l + ( c l - 1 ) = 5 t d q s c k d l l _ d i f f _ m i n t d q s c k d l l _ d i f f _ m a x d i n b d i n b + 1 d i n b + 2 d i n b + 3 d i n b + 4 d i n b + 5 d i n b + 6 d i n b + 7 d i n b d i n b + 1 d i n b + 2 d i n b + 3 d i n b + 4 d i n b + 5 d i n b + 6 d i n b + 7 ddr3 (l) 2 gb sdram nt5c b( c ) 256 m8 f n / nt5cb(c) 128 m16 f p version 1. 6 35 nanya technology cooperation ? 0 4 / 201 4 all rights reserved. dll on/off switching procedure ddr3(l) dll - off mode is entered by setting mr1 bit a0 to 1; this will disable the dll for subsequent operation until a0 bit set back to 0. dll on to dll off procedure to switch from dll on to dll off requir es the frequency to be changed during self - refresh outlined in the following procedure: 1. starting from idle state (all banks pre - charged, all timing fulfilled, and drams on - die termination resistors, rtt, must be in high impedance state before mrs to mr1 to disable the dll). 2. set mr1 bit a0 to 1 to disable the dll. 3. wait tmod. 4. enter self refresh mode; wait until (tcksre) satisfied. 5. change frequency, in guidance with input clock frequency change section. 6. wait until a stable clock is available for at least ( tcksrx) at dram inputs. 7. starting with the self refresh exit command, cke must continuously be registered high until all tmod timings from any mrs command are satisfied. in addition, if any odt features were enabled in the mode registers when self refresh m ode was entered, the odt signal must continuously be registered low until all tmod timings from any mrs command are sat isfied. if both odt features were disabled in the mode registers when self refresh mode was entered, odt signal can be registered low or high. 8. wait txs, and then set mode registers with appropriate values (especially an update of cl, cwl, and wr may be necessary. a zqcl command may also be issued after txs). 9. wait for tmod, and then dram is ready for next command. ddr3 (l) 2 gb sdram nt5c b( c ) 256 m8 f n / nt5cb(c) 128 m16 f p version 1. 6 36 nanya technology cooperation ? 0 4 / 201 4 all rights reserved. dll switch sequence from dll - on to dll - off c k c k t 0 t 1 t a 0 t a 1 t b 0 t c 0 t d 0 t d 1 t e 0 t e 1 m r s 2 ) 1 ) c m d c k e o d t t m o d t f 0 t c k s r e 4 ) t c k s r x 5 ) t x s t m o d n o p s r e 3 ) n o p s r x 6 ) n o p m r s 7 ) n o p v a l i d 8 ) t c k e s r v a l i d 8 ) v a l i d 8 ) t i m e b r e a k d o n o t c a r e n o t e : o d t : s t a t i c l o w i n c a s e r t t _ n o m a n d r t t _ w r i s e n a b l e d , o t h e r w i s e s t a t i c l o w o r h i g h 1 ) s t a r t i n g w i t h i d l e s t a t e , r t t i n h i - z s t a t e . 2 ) d i s a b l e d l l b y s e t t i n g m r 1 b i t a 0 t o 1 . 3 ) e n t e r s r . 4 ) c h a n g e f r e q u e n c y . 5 ) c l o c k m u s t b e s t a b l e a t l e a s t t c k s r x . 6 ) e x i t s r . 7 ) u p d a t e m o d e r e g i s t e r s w i t h d l l o f f p a r a m e t e r s s e t t i n g . 8 ) a n y v a l i d c o m m a n d . ddr3 (l) 2 gb sdram nt5c b( c ) 256 m8 f n / nt5cb(c) 128 m16 f p version 1. 6 37 nanya technology cooperation ? 0 4 / 201 4 all rights reserved. dll off to dll on procedure to switch from dll off to dll on (with requires frequency change) during self - refresh : 1. starting from idle state (all banks pre - charged, all timings fulfilled and drams on - die termination resistors (rtt) must be in high impedance state before self - refresh mode is entered). 2. enter self refresh mode, wait until tcksre satisfied. 3. change frequency, in guidance with input clock frequency change section. 4. wait until a stable is av ailable for at least (tcksrx) at dram inputs. 5. starting with the self refresh exit command, cke must continuously be registered high until tdllk timing from subse - quent dll reset command is satisfied. in addition, if any odt features were enabled in the mod e registers when self refresh mode was entered. the odt signal must continuously be registered low until tdllk timings from subsequent dll reset command is satisfied. if both odt features are disabled in the mode registers when self refresh mode was entere d, odt signal can be registered low or high. 6. wait txs, then set mr1 bit a0 to 0 to enable the dll. 7. wait tmrd, then set mr0 bit a8 to 1 to start dll reset. 8. wait tmrd, then set mode registers with appropriate values (especially an update of cl, cwl, and wr may be necessary. after tmod satisfied from any proceeding mrs command, a zqcl command may also be issued during or after tdllk). 9. wait for tmod, then dram is ready for next command (remember to wait tdllk after dll reset before applying command requirin g a locked dll!). in addition, wait also for tzqoper in case a zqcl command was issued. ddr3 (l) 2 gb sdram nt5c b( c ) 256 m8 f n / nt5cb(c) 128 m16 f p version 1. 6 38 nanya technology cooperation ? 0 4 / 201 4 all rights reserved. dll switch sequence from dll - on to dll - off ck ck t 0 ta 0 ta 1 tb 0 tc 0 tc 1 td 0 te 0 tf 1 tg 0 1 ) cmd cke odt th 0 tcksre tcksrx 4 ) txs tmrd tdllk nop sre 2 ) srx 5 ) mrs 6 ) mrs 7 ) mrs 8 ) valid odtloff + 1 tck 3 ) tmrd valid tckesr time break do not care nop note: odt: static low in case rtt_nom and rtt_wr is enabled, otherwise static low or high 1) starting from idle state. 2) enter sr. 3) change frequency. 4) clock must be stable at least tcksrx. 5) exit sr. 6) set dll-on by mr1 a0="0" 7) start dll reset 8) any valid command ddr3 (l) 2 gb sdram nt5c b( c ) 256 m8 f n / nt5cb(c) 128 m16 f p version 1. 6 39 nanya technology cooperation ? 0 4 / 201 4 all rights reserved. input clock frequency change once the ddr3(l) sdram is initialized, the ddr3(l) sdram require s the clock to be stable during almost all states of normal operation. this means once the clock frequency has been set and is to be in the stable state, the clock period is not allowed to deviate except for what is allowed for by the clock jitter and ssc (spread spectrum clocking) specification. the input clock frequency can be changed from one stable clock rate to another stable clock rate under two conditions: (1) self - refresh mode and (2) precharge power - down mode. outside of these two modes, it is illegal to change the clock frequency. for the first condition, once the ddr3(l) sdram has been successfully placed in to self - refresh mode and tcksre has been satisfied, the state of the clock becomes a dont care. once a dont care, changing the clock fr equency is permissible, provided the new clock frequency is stable prior to tcksrx. when entering and exiting self - refresh mode of the sole purpose of changing the clock frequency. the ddr3(l) sdram input clock frequency is allowed to change only within th e minimum and maximum operating frequency specified for the particular speed grade. the second condition is when the ddr3(l) sdram is in precharge power - down mode (either fast exit mode or slow exit mode). if the rtt_nom feature was enabled in the mode re gister prior to entering precharge power down mode, the odt signal must continuously be registered low ensuring rtt is in an off state. if the rtt_nom feature was disabled in the mode register prior to entering precharge power down mode, rtt will remain in the off state. the odt signal can be registered either low or high in this case. a minimum of tcksre must occur after cke goes low before the clock frequency may change. the ddr3(l) sdram input clock frequency is allowed to change only within the minimum and maximum operating frequency specified for the particular speed grade. during the input clock frequency change, odt and cke must be held at stable low levels. once the input clock frequency is changed, stable new clocks must be provided to the dram tcks rx before precharge power down may be exited; after precharge power down is exited and txp has expired, the dll must be reset via mrs. depending on the new clock frequency additional mrs commands may need to be issued to appropriately set the wr, cl, and c wl with cke continuously registered high. during dll re - lock period, odt must remain low and cke must remain high. after the dll lock time, the dram is ready to operate with new clock frequency. ddr3 (l) 2 gb sdram nt5c b( c ) 256 m8 f n / nt5cb(c) 128 m16 f p version 1. 6 40 nanya technology cooperation ? 0 4 / 201 4 all rights reserved. change frequency during precharge power - down notes: 1. a pplicable for both slow exit and fast exit precharge power - down 2. taofpd and taof must be statisfied and outputs high - z prior to t1; refer to odt timing section for exact requirements 3. if the rtt_nom feature was enabled in the mode register prior to ent ering precharge power down mode, the odt signal must continuously be registered low ensuring rtt is in an off state. if the rtt_nom feature was disabled in the mode register prior to entering precharge power down mode, rtt will remain in the off state. the odt signal can be registered either low or high in this case. ck ck t 0 t 1 t 2 ta 0 tb 0 tc 0 tc 1 td 0 td 1 te 0 cke command dqs , dqs tch tcl tck te 1 tih tis tih tis tcksre tcke tcksrx tchb tclb tckb nop nop nop nop nop mrs nop valid dll reset valid tih tis address odt dq dm high - z high - z taofpd / taof tcpded txp tdllk previous clock frequency new clock frequency frequency change enter precharge power - down mode exit precharge power - down mode ddr3 (l) 2 gb sdram nt5c b( c ) 256 m8 f n / nt5cb(c) 128 m16 f p version 1. 6 41 nanya technology cooperation ? 0 4 / 201 4 all rights reserved. write leveling for better signal integrity, ddr3(l) memory adopted fly by topology for the commands, addresses, control signals, and clocks. the fly by topology has benefits from reducing numb er of stubs and their length but in other aspect, causes flight time skew between clock and strobe at every dram on dimm. it makes it difficult for the controller to maintain tdqss, tdss, and tdsh specification. therefore, the controller should support wr ite leveling in ddr3(l) sdram to compensate the skew. the memory controller can use the write leveling feature and feedback from the ddr3(l) sdram to adjust the dqs - ??? to ck - ?? relationship. the memory controller involved in the leveling must have adjustable delay setting on dqs - ??? to align the rising edge of dqs - ??? with that of the clock at the dram pin. dram asynchronously feeds back ck - ?? , sampled with t he rising edge of dqs - ??? , through the dq bus. the controller repeatedly delays dqs - ??? ? until a transition from 0 to 1 is detected. the dqs - ??? delay established though this exercise would ensure tdqss specification. besides tdqss, tdss, and tdsh spe cification also needs to be fulfilled. one way to achieve this is to combine the actual tdqss in the application with an appropriate duty cycle and jitter on the dqs - ??? ? signals. depending on the actual tdqss in the application, the actual val ues for tdq sl and tdqsh may have to be better than the absolute limits provided in ac timing parameters section in order to satisfy tdss and tdsh specification. a conceptual timing of this scheme is show as below figure. write leveling concept dqs/ ??? driven by the controller during leveling mode must be determined by the dram based on ranks populated. similarly, the dq bus driven by the dram must also be terminated at the controller. a separate d feedback mechanism should be able for each byte lane. the low byte lane s prime dq, dq 0 , carr ies the leveling feedback to the controller across the dram configurations x4/ x8 whereas dq0 indicate s the lower diff_dqs (diff_ldqs) to clock relationship. the high byte lane s prime dq, dq8, provide s the feedback o f the upper diff_dqs (diff_udqs) to clock relationshi p. 0 or 1 0 0 diff _ ck diff _ dqs source diff _ ck diff _ dqs destination dq dq push dqs to capture 0 - 1 transition 0 or 1 1 1 ddr3 (l) 2 gb sdram nt5c b( c ) 256 m8 f n / nt5cb(c) 128 m16 f p version 1. 6 42 nanya technology cooperation ? 0 4 / 201 4 all rights reserved. dram setting for write leveling and dram termination unction in that mode dram enters into write leveling mode if a7 in mr1 set high and after finishing leveling, dram exits from write leveling mode if a7 in mr1 set low. note that in write leveling mode, only dqs/ ??? terminations are activated and deactivated via odt pin not like normal operation. mr setting involved in the leveling procedure function mr1 enable disable write leveling enable a7 1 0 output buffer mode (qoff) a12 0 1 dram termination function in the leveling mode odt pin at dram dqs/ ??? termination dq s termination de - asserted off off asserted on off note: in write leveling mode with its output buffer disabled (mr1[bit7]=1 with mr1[bit12]=1) all rtt_nom settings are allowed; in write leveling mode with its output buffer enabled (mr1[bit7]=1 with mr1[bit12]=0) only rtt_nom settings of rzq/2, rzq/4, and rzq/6 are allowed. procedure description memory controller initiates leveling m ode of all drams by setting bit 7 of mr1 to 1. with entering write leveling mode, the dq pins are in undefined driving mode. during write leveling mode, only nop or deselect commands are allowed. as well as an mrs command to exit write leveling mode. since the controller levels one rank at a time, the output of other rank must be disabled by setting mr1 bit a12 to 1. controller may assert odt after tmod, time at which dram is ready to accept the odt signal. controller may drive dqs low and ??? high after a delay of twldqsen, at which time dram has applied on - die termination on these signals. after tdqsl and twlmrd co ntroller provides a single dqs, ???? edge which is used by the dram to sample ck C ?? driven from controller. twlmrd (max) timing is controller d ependent. dram samples ck - ?? status with rising edge of dqs and provides feedback on all the dq bits asynchronously after twlo timing. there is a dq output uncertainty of twloe defined to allow mismatch on dq bits; there are no read strobes (dqs/dqs) ne eded for these dqs. controller samples incoming dq and decides to increment or decrement dqs C ??? delay setting and launches the next dqs/ ??? pulse after some time, which is controller dependent. once a 0 to 1 transition is detected, the controller locks dqs C ??? delay setting and write leveling is achieved for the device. the following figure describes the timing diagram and parameters for the overall write leveling procedure. ddr3 (l) 2 gb sdram nt5c b( c ) 256 m8 f n / nt5cb(c) 128 m16 f p version 1. 6 43 nanya technology cooperation ? 0 4 / 201 4 all rights reserved. timing details of write leveling sequence (for information. only support prim e dq) dqs - ??? ?? ?? write leveling mode exit the following sequence describes how write leveling mode should be exited: 1. after the last rising strobe edge (see ~t0), stop drivin g the strobe signals (see ~tc0). note: from now on, dq pins are in undefined driving mode, and will remain undefined, until tmod after the respective mr command (te1). 2. drive odt pin low (tis must be satisfied) and keep it low (see tb0). 3. after the rtt is switched off, disable write level mode via mrs command (see tc2). 4. af ter tmod is satisfied (te1), any valid command may be registered. (mr commands may be issued after tmrd (td1). nop nop nop nop nop nop nop nop nop ck ck cmd odt di ff _ dqs prime dq late re ma ini ng dqs tmod twlmr d twlo twls t wlh twloe twls t wlh t wlo nop m rs tdqsh tdqsl tdqsh t dqsl t 1 t 2 time break do not care one pri me dq : earl y re ma ini ng dqs twlo t wlo undefined driving mode twloe twlo t wlo all dqs are prime : late re ma ini ng dqs earl y re ma ini ng dqs twlmrd twlo t wlo t wloe twldqsen nop note: 1. dram has the option to drive leveling feedback on a prime dq or all dqs. if feedback is driven only on one dq, the remaining dqs must be driven low as shown in above figure, and maintained at this state through out the leveling procedure. 2. mrs: load mr1 to enter write leveling mode 3. nop: nop or deselect 4. diff_dqs is the differential data strobe (dqs, ??? ). timing reference points are the zero crossings. dqs is shown with solid line, ??? is shown with dotted line. 6. dqs/ ??? needs to fulfill minimum pulse width requirements tdqsh(min) and tdqsl(min) as defined for regular writes; the max pulse width is system dependent. ddr3 (l) 2 gb sdram nt5c b( c ) 256 m8 f n / nt5cb(c) 128 m16 f p version 1. 6 44 nanya technology cooperation ? 0 4 / 201 4 all rights reserved. timing detail of write leveling exit extended temperature usage nanya s dd r3(l) sdram supports the optional extended temperature range of 0c to +95c, tc. thus, the srt and asr options must be used at a minimum. the extended temperature range dram must be refreshed externally at 2x (double refresh) anytime the case temperature is above +85c ( in supporting temperature range ). the external refreshing requirement is accomplished by reducing the refresh period from 64ms to 32ms. however, self refresh mode requires either asr or srt to support the extended temperature. thus either a sr or srt must be enabled when tc is above +85c or self refresh cannot be used until the case temperature is at or below +85c. mode register description field bits description asr mr2(a6) auto self - refresh (asr) when enabled, ddr3(l) sdram automatical ly provides self - refresh power management functions for all supported operating temperature values. if not enabled, the srt bit must be programmed to indicate t oper during subsequent self - refresh operation. 0 = manual sr reference (srt) 1 = asr enable sr t mr2(a7) self - refresh temperature (srt) range if asr = 0, the srt bit must be programmed to indicate t oper during subsequent self - refresh operation. if asr = 1, srt bit must be set to 0. 0 = normal operating temperature range 1 = extended operating tempe rature range ck ck t 0 t 1 ta 0 tc 0 tc 1 tc 2 td 1 te 1 cmd ba tis tmod tmrd odt rtt _ dqs _ dqs dqs _ dqs result = 1 twlo dq rtt _ nom td 0 te 0 t 2 tb 0 taofmin taofmax transitioning time break do not care undefined driving mode nop nop nop nop nop nop nop mrs nop valid nop valid mr 1 valid valid todtloff ddr3 (l) 2 gb sdram nt5c b( c ) 256 m8 f n / nt5cb(c) 128 m16 f p version 1. 6 45 nanya technology cooperation ? 0 4 / 201 4 all rights reserved. auto self - refresh mode - asr mode ddr3(l) sdram provides an auto - refresh mode (asr) for application ease. asr mode is enabled by setting mr2 bit a6=1 and mr2 bit a7=0. the dram will manage self - refresh entry in either the normal or extended temperature ranges. in this mode, the dram will also manage self - refresh power consumption when the dram operating temperature changes, lower at low temperatures and higher at high temperatures. if the asr option is not supported by dram, mr2 bit a6 must s et to 0. if the asr option is not enabled (mr2 bit a6=0), the srt bit (mr2 bit a7) must be manually programmed with the operating temperature range required during self - refresh operation. support of the asr option does not automatically imply support of th e extended temperature range. self - refresh temperature range - srt srt applies to devices supporting extended temperature range only. if asr=0, the self - refresh temperature (srt) range bit must be programmed to guarantee proper self - refresh operation. if s rt=0, then the dram will set an appropriate refresh rate for self - refresh operation in the normal temperature range. if srt=1, then the dram will set an appropriate, potentially different, refresh rate to allow self - refresh operation in either the normal o r extended temperature ranges. the value of the srt bit can effect self - refresh power consumption, please refer to idd table for details. self - refresh mode summary mr2 a[6] mr2 a[7] self - refresh operation allowed operating temperature range for self - ref resh mode 0 0 self - refresh rate appropriate for the normal temperature range normal 1 0 1 self - refresh appropriate for either the normal or extended temperature ranges. the dram must support extended temperature range. the value of the srt bit can effect self - refresh power consumption, please refer to the idd table for details. normal and extended 2 1 0 asr enabled (for devices supporting asr and normal temperature range). self - refresh power consumption is temperature dependent. normal 1 1 0 asr enabled (for devices supporting asr and extended temperature range). self - refresh power consumption is temperature dependent. normal and extended 2 1 1 illegal notes: 1. the normal range depends on product s grade. - commercial grade = 0 ~ 8 5 - industrial grade ( - i ) = - 40 ~ 8 5 - automotive grade 2 ( - h ) = - 40 ~ 8 5 - automotive grade 3 ( - a ) = - 40 ~ 8 5 2 . the normal and extended range depends on product s grade. - commercial grade = 0 ~ 95 - industrial grade ( - i ) = - 40 ~ 9 5 - automotive grade 2 ( - h ) = - 40 ~ 10 5 - automotive grade 3 ( - a ) = - 40 ~ 9 5 ddr3 (l) 2 gb sdram nt5c b( c ) 256 m8 f n / nt5cb(c) 128 m16 f p version 1. 6 46 nanya technology cooperation ? 0 4 / 201 4 all rights reserved. mpr mr3 register definition mr3 a[2] mr3 a[1:0] function 0 don't care (0 or 1) normal operation, no mpr transaction. all subsequent reads will come from dram array. all subsequent writes will go to dram array. 1 see the following table enable mpr mo de, subsequent rd/rda commands defined by mr3 a[1:0]. mpr functional description ? one bit wide logical interface via all dq pins during read operation. ? register read on x8: ? dq [0] drives information from mpr. ? dq [7:1] either drive the same information as d q [0], or they drive 0. ? addressing during for multi purpose register reads for all mpr agents: ? ba [2:0]: dont care. ? a [1:0]: a [1:0] must be equal to 00. data read burst order in nibble is fixed. ? a[2]: for bl=8, a[2] must be equal to 0, burst order is f ixed to [0,1,2,3,4,5,6,7]; for burst chop 4 cases, the burst order is switched on nibble base, a[2]=0, burst order: 0,1,2,3, a[2]=1, burst order: 4,5,6,7. *) ? a [9:3]: dont care. ? a10/ap: dont care. ? a12/bc: selects burst chop mode on - the - fly, if enabled wi thin mr0 ? a11, a13: dont care. ? regular interface functionality during register reads: ? support two burst ordering which are switched with a2 and a[1:0]=00. ? support of read burst chop (mrs and on - the - fly via a12/bc). ? all other address bits (remaining column addresses bits including a10, all bank address bits) will be ignored by the ddr3(l) sdram. ? regular read latencies and ac timings apply. ? dll must be locked prior to mpr reads. note: burst order bit 0 is assigned to lsb and burst order bit 7 is assigned to m sb of the selected mpr agent. ddr3 (l) 2 gb sdram nt5c b( c ) 256 m8 f n / nt5cb(c) 128 m16 f p version 1. 6 47 nanya technology cooperation ? 0 4 / 201 4 all rights reserved. mpr register address definition the following table provide an overview of the available data location, how they are addressed by mr3 a[1:0] during a mrs to mr3, and how their individual bits are mapped into the burst order b its during a multi purpose register read. mpr mr3 register definition mr3 a[2] mr3 a[1:0] function burst length read address a[2:0] burst order and data pattern 1 00 read predefined pattern for system calibration bl8 000 burst order 0,1,2,3,4,5,6,7 pre - d efined data pattern [0,1,0,1,0,1,0,1] bc4 000 burst order 0,1,2,3 pre - defined data pattern [0,1,0,1] bc4 100 burst order 4,5,6,7 pre - defined data pattern [0,1,0,1] 1 01 rfu bl8 000 burst order 0,1,2,3,4,5,6,7 bc4 000 burst order 0,1,2,3 bc 4 100 burst order 4,5,6,7 1 10 rfu bl8 000 burst order 0,1,2,3,4,5,6,7 bc4 000 burst order 0,1,2,3 bc4 100 burst order 4,5,6,7 1 11 rfu bl8 000 burst order 0,1,2,3,4,5,6,7 bc4 000 burst order 0,1,2,3 bc4 100 burst order 4,5,6,7 note: bur st order bit 0 is assigned to lsb and the burst order bit 7 is assigned to msb of the selected mpr agent. active command the active command is used to open (or activate) a row in a particular bank for subsequent access. the value on the ba0 - ba2 inputs se lects the bank, and the addresses provided on inputs a0 - a1 4 selects the row. these rows remain active (or open) for accesses until a precharge command is issued to that bank. a precharge command must be issued before opening a differ ent row in the same ban k. ddr3 (l) 2 gb sdram nt5c b( c ) 256 m8 f n / nt5cb(c) 128 m16 f p version 1. 6 48 nanya technology cooperation ? 0 4 / 201 4 all rights reserved. precharge command the precharge command is used to deactivate the open row in a particular bank or the open row in all banks. the bank(s) will be available for a subsequent row activation a specified time (trp) after the precharge command is issued, ex cept in the case of concurrent auto precharge, where a read or write command to a different bank is allowed as long as it does not interrupt the data transfer in the current bank and does not violate any other timing parameters. once a bank has been precha rged, it is in the idle state and must be activated prior to any read or write commands being issued to that bank. a precharge command is allowed if there is no open row in that bank (idle bank) or if the previously open row is already in the process of pr echarging. however, the precharge period will be determined by the last precharge command issued to the bank. ddr3 (l) 2 gb sdram nt5c b( c ) 256 m8 f n / nt5cb(c) 128 m16 f p version 1. 6 49 nanya technology cooperation ? 0 4 / 201 4 all rights reserved. read operation read burst operation during a read or write command ddr3(l) will support bc4 and bl8 on the fly using address a12 during the rea d or write (auto precharge can be enabled or disabled). a12=0, bc4 (bc4 = burst chop, tccd=4) a12=1, bl8 a12 will be used only for burst length control, not a column address. read burst operation rl=5 (al=0, cl=5, bl=8) read burst operation rl = 9 ( al=4, cl=5, bl=8) c k c k t 0 t 1 t 3 t 5 t 6 t 7 t 9 c l = 5 d q s , d q s t 2 t 4 t 8 t 1 0 r e a d n o p c m d n o p n o p n o p n o p n o p n o p n o p n o p n o p b a n k c o l n a d d r e s s d o u t n d o u t n + 1 d o u t n + 2 d o u t n + 3 d o u t n + 4 d o u t n + 5 d o u t n + 6 d o u t n + 7 d q r l = a l + c l t r p r e t r p s t c k c k t 0 t 1 t 3 t 5 t 6 t 7 t 9 c l = 5 d q s , d q s t 2 t 4 t 8 t 1 0 r e a d n o p c m d n o p n o p n o p n o p n o p n o p n o p n o p n o p b a n k c o l n a d d r e s s d o u t n d o u t n + 1 d o u t n + 2 d o u t n + 3 d q r l = a l + c l t r p r e a l = 4 ddr3 (l) 2 gb sdram nt5c b( c ) 256 m8 f n / nt5cb(c) 128 m16 f p version 1. 6 50 nanya technology cooperation ? 0 4 / 201 4 all rights reserved. read timing definitions read timing is shown in the following figure and is applied when the dll is enabled and locked. rising data strobe edge parameters: ? tdqsck min/max describes the allowed range for a rising data strobe edge relative to ck, ?? . ? tdqsck is the actual position of a rising strobe edge relative to ck, ?? . ? tqsh describes the dqs, ??? differential output high time. ? tdqsq describes the latest valid transition of the associated dq pins. ? tqh describes the earliest invalid transition o f the associated dq pins. fal ling data strobe edge parameters: ? tqsl describes the dqs, ??? differential output low time. ? tdqsq describes the latest valid transition of the associated dq pins. ? tqh describes the earliest invalid transition of the associate d dq pins. ddr3 (l) 2 gb sdram nt5c b( c ) 256 m8 f n / nt5cb(c) 128 m16 f p version 1. 6 51 nanya technology cooperation ? 0 4 / 201 4 all rights reserved. read timing; clock to data strobe relationship clock to data strobe relationship is shown in the following figure and is applied when the dll is enabled and locked. rising data strobe edge parameters: ? tdqsck min/max describes the allowed range for a rising data strobe edge relative to ck and ?? . ? tdqsck is the actual position of a rising strobe edge relative to ck and ?? . ? tqsh describes the data strobe high pulse width. falling data strobe edge parameters: ? tqsl describes the data strobe low pulse width. clock to data strobe relationship note s: 1. within a burst, rising strobe edge is not necessarily fixed to be always at tdqsck(min) or tdqsck(max). instead, rising strob e edge can vary between tdqsck(min) and tdqsck(max). 2. the dqs, ??? differential output high time is defined by tqsh and th e dqs, ??? differential output low time is defined by tqsl. 3. likewise, tlz(dqs)min and thz(dqs)min are not tied to tdqsckmin (early strobe case) and tlz(dqs)max and thz(dqs)max are not tied to tdqsckmax (late strobe case). 4. the minimum pulse width of r ead preamble is defined by trpre(min). 5. the maximum read postamble is bound by tdqsck(min) plus tqsh(min) on the left side and thzdsq(max) on the right side. 6. the minimum pulse width of read postamble is defined by trpst(min). 7. the maximum read pream ble is bound by tlzdqs(min) on the left side and tdqsck(max) on the right side . ck ck rl measured to this point dqs , dqs early strobe dqs , dqs late strobe tlz ( dqs ) min tlz ( dqs ) max trpre trpre tdqsckmin tdqsckmax tqsh tqsl trpst trpst thz ( dqs ) min thz ( dqs ) max ddr3 (l) 2 gb sdram nt5c b( c ) 256 m8 f n / nt5cb(c) 128 m16 f p version 1. 6 52 nanya technology cooperation ? 0 4 / 201 4 all rights reserved. read timing; data strobe to data relationship the data strobe to data relationship is shown in the following figure and is applied when the dll and enabled and locked. rising data strobe edge parameters: ? tdqsq describes the latest valid transition of the associated dq pins. ? tqh describes the earliest invalid transition of the associated dq pins. falling data strobe edge parameters: ? tdqsq describes the latest valid transition of the associated dq pins. ? tqh describes the earliest invalid transition of the associated dq pins. ? tdqsq; both rising/falling edges of dqs, no tac defined data strobe to data relationship dout n + 6 dout n + 7 trpst ck ck t 0 t 1 t 3 t 5 t 6 t 7 t 9 dqs , dqs t 2 t 4 t 8 read nop cmd nop nop nop nop nop nop nop nop bank col n address dout n + 1 dout n + 2 dout n + 3 dout n + 4 dout n + 5 dq ( last data valid ) rl = al + cl trpre dout n + 6 dout n + 7 dout n dout n + 1 dout n + 2 dout n + 3 dout n + 4 dout n + 5 tlz ( dq ) min valid data thz ( dq ) min tdqsqmax valid data tqh tqh dout n tdqsqmin dq ( first data no longer valid ) all dq collectively ddr3 (l) 2 gb sdram nt5c b( c ) 256 m8 f n / nt5cb(c) 128 m16 f p version 1. 6 53 nanya technology cooperation ? 0 4 / 201 4 all rights reserved. read to read (cl=5, al=0) t 1 1 t 1 0 n o p n o p d o u t n + 6 d o u t n + 7 t r p s t c k c k t 0 t 1 t 3 t 5 t 6 t 7 t 9 t 2 t 4 t 8 n o p c m d n o p n o p r e a d n o p n o p n o p n o p n o p a d d r e s s d o u t n + 1 d o u t n + 2 d o u t n + 3 d o u t n + 4 d o u t n + 5 t c c d t r p r e d o u t n t 1 2 n o p t 1 3 n o p r l = 5 b a n k c o l b r e a d d o u t b + 6 d o u t b + 7 d o u t b + 1 d o u t b + 2 d o u t b + 3 d o u t b + 4 d o u t b + 5 d o u t b r l = 5 d q s , d q s d q r e a d ( b l 8 ) t o r e a d ( b l 8 ) n o p n o p t r p s t n o p c m d n o p n o p r e a d n o p n o p n o p n o p n o p a d d r e s s d o u t n + 1 d o u t n + 2 d o u t n + 3 t c c d t r p r e d o u t n n o p n o p r l = 5 b a n k c o l b r e a d d o u t b + 1 d o u t b + 2 d o u t b + 3 d o u t b r l = 5 d q s , d q s d q r e a d ( b l 4 ) t o r e a d ( b l 4 ) t r p r e t r p s t r e a d b a n k c o l n r e a d b a n k c o l n ddr3 (l) 2 gb sdram nt5c b( c ) 256 m8 f n / nt5cb(c) 128 m16 f p version 1. 6 54 nanya technology cooperation ? 0 4 / 201 4 all rights reserved. read to write (cl=5, al=0; cwl=5, al=0) t 1 1 t 1 0 n o p d o u t n + 6 d o u t n + 7 t w p s t c k c k t 0 t 1 t 3 t 5 t 6 t 7 t 9 t 2 t 4 t 8 n o p c m d n o p n o p w r i t e a d d r e s s d o u t n + 1 d o u t n + 2 d o u t n + 3 d o u t n + 4 d o u t n + 5 r e a d t o w r i t e c o m m a n d d e l a y = r l + t c c d + 2 t c k - w l t r p r e d o u t n t 1 2 n o p t 1 3 n o p r l = 5 b a n k c o l b d o u t b + 7 d o u t b + 1 d o u t b + 2 d o u t b + 3 d o u t b + 4 d o u t b + 5 w l = 5 d q s , d q s d q r e a d ( b l 8 ) t o w r i t e ( b l 8 ) n o p t w p s t n o p c m d n o p n o p n o p a d d r e s s d o u t n + 1 d o u t n + 2 d o u t n + 3 r e a d t o w r i t e c o m m a n d d e l a y = r l + t c c d / 2 + 2 t c k - w l t r p r e d o u t n n o p n o p r l = 5 r e a d d o u t b + 1 d o u t b + 2 d o u t b + 3 w l = 5 d q s , d q s r e a d ( b l 4 ) t o w r i t e ( b l 4 ) t w p r e t r p s t t 1 4 t 1 5 n o p n o p t w r p r e t r p s t b a n k c o l n r e a d n o p n o p n o p n o p n o p n o p d q n o p n o p t b l = 4 c l o c k s t w r t w t r r e a d b a n k c o l n w r i t e b a n k c o l b n o p d o u t b n o p n o p n o p n o p d o u t b d o u t b + 6 ddr3 (l) 2 gb sdram nt5c b( c ) 256 m8 f n / nt5cb(c) 128 m16 f p version 1. 6 55 nanya technology cooperation ? 0 4 / 201 4 all rights reserved. read to read (cl=5, al=0) t 1 1 t 1 0 n o p n o p d o u t n + 6 d o u t n + 7 t r p s t c k c k t 0 t 1 t 3 t 5 t 6 t 7 t 9 t 2 t 4 t 8 n o p c m d n o p n o p n o p n o p n o p n o p n o p a d d r e s s d o u t n + 1 d o u t n + 2 d o u t n + 3 d o u t n + 4 d o u t n + 5 t c c d t r p r e d o u t n t 1 2 n o p t 1 3 n o p r l = 5 r e a d d o u t b + 1 d o u t b + 2 d o u t b + 3 d o u t b r l = 5 d q s , d q s d q r e a d ( b l 8 ) t o r e a d ( b c 4 ) n o p n o p t r p s t n o p c m d n o p n o p n o p n o p n o p n o p n o p a d d r e s s d o u t n + 1 d o u t n + 2 d o u t n + 3 t c c d t r p r e d o u t n n o p n o p r l = 5 r e a d r l = 5 d q s , d q s r e a d ( b c 4 ) t o r e a d ( b l 8 ) t r p r e t r p s t d q r e a d b a n k c o l n r e a d b a n k c o l n r e a d b a n k c o l b r e a d b a n k c o l b d o u t b + 6 d o u t b + 7 d o u t b + 1 d o u t b + 2 d o u t b + 3 d o u t b + 4 d o u t b + 5 d o u t b ddr3 (l) 2 gb sdram nt5c b( c ) 256 m8 f n / nt5cb(c) 128 m16 f p version 1. 6 56 nanya technology cooperation ? 0 4 / 201 4 all rights reserved. read to write (cl=5, al=0; cwl=5, al=0) t 1 1 t 1 0 n o p n o p d o u t n + 6 d o u t n + 7 t r p s t c k c k t 0 t 1 t 3 t 5 t 6 t 7 t 9 t 2 t 4 t 8 n o p c m d n o p n o p w r i t e a d d r e s s d o u t n + 1 d o u t n + 2 d o u t n + 3 d o u t n + 4 d o u t n + 5 t r p r e d o u t n t 1 2 n o p t 1 3 n o p r l = 5 r e a d d o u t b + 1 d o u t b + 2 d o u t b + 3 w l = 5 d q s , d q s d q n o p n o p t w p s t n o p c m d n o p n o p n o p a d d r e s s d o u t n + 1 d o u t n + 2 d o u t n + 3 r e a d t o w r i t e c o m m a n d d e l a y = r l + t c c d / 2 + 2 t c k - w l t r p r e d o u t n n o p n o p r l = 5 r e a d w l = 5 d q s , d q s r e a d ( b l 4 ) t o w r i t e ( b l 8 ) t w p r e t r p s t d q r e a d b a n k c o l n r e a d b a n k c o l n n o p b a n k c o l b w r i t e b a n k c o l b d o u t b + 6 d o u t b + 7 d o u t b + 1 d o u t b + 2 d o u t b + 3 d o u t b + 4 d o u t b + 5 d o u t b n o p n o p n o p n o p r e a d ( b l 8 ) t o w r i t e ( b c 4 ) n o p n o p n o p n o p t w p s t t w p r e d o u t b r e a d t o w r i t e c o m m a n d d e l a y = r l + t c c d + 2 t c k - w l ddr3 (l) 2 gb sdram nt5c b( c ) 256 m8 f n / nt5cb(c) 128 m16 f p version 1. 6 57 nanya technology cooperation ? 0 4 / 201 4 all rights reserved. write operation ddr3(l) burst operation during a read or write command, ddr3(l) will support bc4 and bl8 on the fly using address a12 during the read or write (auto p recharge can be enabled or disabled). a12=0, bc4 (bc4 = burst chop, tccd=4) a12=1, bl8 a12 is used only for burst length control, not as a column address. write timing violations motivation generally, if timing parameters are violated, a complete reset/i nitialization procedure has to be initiated to make sure the dram works properly. however, it is desirable for certain minor violations that the dram is guaranteed not to hang up and errors be limited to that particular operation. for the following, it w ill be assumed that there are no timing violations with regard to the write command itself (including odt, etc.) and that it does satisfy all timing requirements not mentioned below. data setup and hold violations should the strobe timing requirements (td s, tdh) be violated, for any of the strobe edges associated with a write burst, then wrong data might be written to the memory location addressed with the offending write command. subsequent reads from that location might result in unpredictable read data , however, the dram will work properly otherwise. strobe to strobe and strobe to clock violations should the strobe timing requirements (tdqsh, tdqsl, twpre, twpst) or the strobe to clock timing requirements (tdss, tdsh, tdqss) be violated, for any of the strobe edges associated with a write burst, then wrong data might be written to the memory location addressed with the offending write command. subsequent reads from that loc ation might result in unpredict able read data, however the dram will work properl y otherwise. write timing parameters this drawing is for example only to enumerate the strobe edges that belong to a write burst. no actual timing violations are shown here. for a valid burst all timing parameters for each edge of a burst need to be sa tisfied (not only for one edge - as shown). ddr3 (l) 2 gb sdram nt5c b( c ) 256 m8 f n / nt5cb(c) 128 m16 f p version 1. 6 58 nanya technology cooperation ? 0 4 / 201 4 all rights reserved. write timing definition note: 1. bl=8, wl=5 (al=0, cwl=5). 2. din n = data in from column n. 3. nop commands are shown for ease of illustration; other command may be valid at these times. 4. bl8 setting activated by eithe r mr0 [a1:0=00] or mr0 [a1:0=01] and a12 = 1 during write command at t0. 5. tdqss must be met at each rising clock edge. t n c k c k t 0 t 1 t 3 t 5 t 6 t 7 t 9 t 2 t 4 t 8 n o p c m d n o p n o p a d d r e s s d q n o p w l = a l + c w l n o p n o p d i n n + 6 d i n n + 7 d i n n + 1 d i n n + 2 d i n n + 3 d i n n + 4 d i n n + 5 d i n n t d q s s t d s h t d q s l t d s s t w p s t ( m i n ) t d q s l ( m i n ) t d s s t d s s t d s s t d s s d q t d s h t d q s h t d q s l t d s s t d q s h t w p r e ( m i n ) t d s s t d s h t d q s h t d s h t d s h t d s s t d s s t d s s d q d i n n + 6 d i n n + 7 d i n n + 1 d i n n + 2 d i n n + 3 d i n n + 4 d i n n + 5 d i n n t d s h t d q s h t d q s h t d s h t d q s h t d s h t d s h n o p t d q s h t w p r e ( m i n ) w r i t e b a n k c o l n t w p r e ( m i n ) t d q s h n o p t d s s t d q s l t d s s t d s s n o p t d s h t d s h d i n n + 6 d i n n + 7 d i n n + 1 d i n n + 2 d i n n + 3 d i n n + 4 d i n n + 5 d i n n t d q s h t d s h n o p t d s s t d s s t d q s l ( m i n ) t w p s t ( m i n ) t d q s l ( m i n ) t w p s t ( m i n ) t d q s s d q s , d q s ( t d q s s m i n ) d q s , d q s ( t d q s s n o m i n a l ) d q s , d q s ( t d q s s m a x ) ddr3 (l) 2 gb sdram nt5c b( c ) 256 m8 f n / nt5cb(c) 128 m16 f p version 1. 6 59 nanya technology cooperation ? 0 4 / 201 4 all rights reserved. write to write (wl=5; cwl=5, al=0) t 1 1 t 1 0 n o p d o u t n + 7 c k c k t 0 t 1 t 3 t 5 t 6 t 7 t 9 t 2 t 4 t 8 n o p c m d n o p n o p n o p a d d r e s s d o u t n + 1 d o u t n + 2 d o u t n + 3 d o u t n + 5 t c c d t w p r e t 1 2 n o p t 1 3 n o p w l = 5 d o u t b + 6 d o u t b + 7 d o u t b + 1 d o u t b + 2 d o u t b + 3 d o u t b + 5 w l = 5 d q s , d q s d q w r i t e ( b l 8 ) t o w r i t e ( b l 8 ) n o p t w p s t n o p c m d n o p n o p n o p a d d r e s s d o u t n + 1 d o u t n + 2 d o u t n + 3 t c c d t r p r e n o p n o p w l = 5 r e a d d o u t b + 1 d o u t b + 2 d o u t b + 3 w l = 5 d q s , d q s w r i t e ( b c 4 ) t o w r i t e ( b c 4 ) t w p r e t w p s t t w p s t b a n k c o l n w r i t e n o p n o p n o p n o p n o p w r i t e d q w r i t e b a n k c o l n w r i t e b a n k c o l b n o p b a n k c o l b d o u t n n o p n o p n o p n o p d o u t n + 4 d o u t n + 6 d o u t b d o u t b + 4 t b l = 4 t w r t w t r t b l = 4 t w r t w t r d o u t n d o u t b ddr3 (l) 2 gb sdram nt5c b( c ) 256 m8 f n / nt5cb(c) 128 m16 f p version 1. 6 60 nanya technology cooperation ? 0 4 / 201 4 all rights reserved. write to read (rl=5, cl=5, al=0; wl=5, cwl=5, al=0; bl=4) t 1 1 t 1 0 n o p d o u t n + 7 c k c k t 0 t 1 t 3 t 5 t 6 t 7 t 9 t 2 t 4 t 8 n o p c m d n o p n o p n o p a d d r e s s d o u t n + 1 d o u t n + 2 d o u t n + 3 d o u t n + 5 t w p r e t 1 2 n o p t 1 3 r e a d w l = 5 d q s , d q s d q w r i t e ( b l 8 ) t o r e a d ( b c 4 / b l 8 ) n o p n o p c m d n o p n o p n o p a d d r e s s d o u t n + 1 d o u t n + 2 d o u t n + 3 t r p r e d o u t n n o p r e a d w l = 5 d q s , d q s w r i t e ( b c 4 ) t o r e a d ( b c 4 / b l 8 ) t w p s t b a n k c o l n w r i t e n o p n o p n o p n o p n o p n o p d q w r i t e b a n k c o l n n o p n o p b a n k c o l b d o u t n n o p n o p n o p n o p d o u t n + 4 d o u t n + 6 t w t r r l = 5 t b l = 4 t w p s t b a n k c o l b t w t r r l = 5 ddr3 (l) 2 gb sdram nt5c b( c ) 256 m8 f n / nt5cb(c) 128 m16 f p version 1. 6 61 nanya technology cooperation ? 0 4 / 201 4 all rights reserved. write to write (wl=5, cwl=5, al=0) t 1 1 t 1 0 n o p d o u t n + 7 c k c k t 0 t 1 t 3 t 5 t 6 t 7 t 9 t 2 t 4 t 8 n o p c m d n o p n o p n o p a d d r e s s d o u t n + 1 d o u t n + 2 d o u t n + 3 d o u t n + 5 t c c d t w p r e t 1 2 n o p t 1 3 n o p w l = 5 d o u t b + 1 d o u t b + 2 w l = 5 d q s , d q s d q w r i t e ( b l 8 ) t o w r i t e ( b c 4 ) n o p t w p s t n o p c m d n o p n o p n o p a d d r e s s d o u t n + 1 d o u t n + 2 d o u t n + 3 t c c d t r p r e d o u t n n o p n o p w l = 5 r e a d d o u t b + 1 d o u t b + 2 d o u t b + 3 w l = 5 d q s , d q s w r i t e ( b c 4 ) t o w r i t e ( b l 8 ) t w p r e t w p s t t w p s t b a n k c o l n w r i t e n o p n o p n o p n o p n o p w r i t e d q w r i t e b a n k c o l n w r i t e b a n k c o l b n o p b a n k c o l b d o u t n n o p n o p n o p n o p d o u t n + 4 d o u t n + 6 d o u t b t b l = 4 t w r t w t r t b l = 4 t w r t w t r d o u t b + 3 d o u t b + 6 d o u t b + 7 d o u t b + 3 d o u t b + 5 d o u t b + 4 d o u t b ddr3 (l) 2 gb sdram nt5c b( c ) 256 m8 f n / nt5cb(c) 128 m16 f p version 1. 6 62 nanya technology cooperation ? 0 4 / 201 4 all rights reserved. refresh command the refresh command (ref) is used during normal operation of the ddr3(l) sdrams. this command is not persistent, so it must be issued each time a refresh is required. the ddr3(l) sdram requires refresh cycles at an average periodic inter val of trefi. when ?? , ra? , and ?a? are held low and we high at the rising edge of the clock, the chip enters a refresh cycle. all banks of the sdram must be precharged and idle for a minimum of the precharge time trp(min) before the refresh command can be applied. the refre sh addressing is generated by the internal refresh controller. this makes the address bits dont care during a refresh command. an internal address counter suppliers the address during the refresh cycle. no control of the external address bus is required once this cycle has started. when the refresh cycle has completed, all banks of the sdram will be in the precharged (idle) state. a delay between the refresh command and the next valid command, except nop or des, must be greater than or equal to the minim um refresh cycle time trfc(min) as shown in the following figure. in general, a refresh command needs to be issued to the ddr3(l) sdram regularly every trefi interval. to allow for improved efficiency in scheduling and switching between tasks, some flexi bility in the absolute refresh interval is provided. a maximum of 8 refresh commands can be postponed during operation of the ddr3(l) sdram, meaning that at no point in time more than a total of 8 refresh commands are allowed to be postponed. in case that 8 refresh commands are postponed in a row, the result ing maximum interval between the surrounding refresh commands is limited to 9 x trefi. a maximum of 8 additional refresh commands can be issued in advance (pulled in), with each one reducing the numbe r of regular refresh commands required later by one. note that pulling in more than 8 refresh commands in advance does not further reduce the number of regular refresh commands required later, so that the resulting maximum interval between two surrounding refresh command is limited to 9 x trefi. before entering self - refresh mode, all postponed refresh commands must be executed. self - refresh entry/exit timing postponing refresh commands (example) ck ck t 0 t 1 ta 0 tb 0 tb 1 tb 3 ta 1 tb 2 nop cmd nop ref valid nop ref nop valid valid valid valid ref tc 0 tc 1 valid trfc trfc ( min ) trefi ( max , 9 x trefi ) dram must be idle dram must be idle time break 9 x t r e f i t r e f i t r e f i 8 r e f - c o m m a n d p o s t p o n e d t ddr3 (l) 2 gb sdram nt5c b( c ) 256 m8 f n / nt5cb(c) 128 m16 f p version 1. 6 63 nanya technology cooperation ? 0 4 / 201 4 all rights reserved. pulled - in refresh commands (example) s elf - refresh opera tion the self - refresh command can be used to retain data in the ddr3(l) sdram, even if the reset of the system is powered down. when in the self - refresh mode, the ddr3(l) sdram retains data without external clocking. the ddr3(l) sdram device has a built - in timer to accommodate self - refresh operation. the self - refresh entry (sre) command is defined by having ?? , ra? , ?a? , and ??e held low with we high at the rising edge of the clock. before issuing the self - refreshing - entry command, the ddr3(l) sdram must b e idle with all ba nk precharge state with trp sat isfied. also, on - die termination must be turned off before issuing self - refresh - entry command, by either registering odt pin low odtl + 0.5tck prior to the self - refresh entry command or using mrs to mr1 co mmand. once the self - refresh entry com mand is registered, cke must be held low to keep the device in self - refresh mode. during normal operation (dll on), mr1 (a0=0), the dll is automatically disabled upon entering self - refresh and is automatically enabled (including a dll - reset) upon exiting self - refresh. when the ddr3(l) sdram has entered self - refresh mode, all of the external control signals, except cke and re?et , are dont care. for proper self - refresh operation, all power supply and reference pins (v dd, vddq, vss, vssq, vrefca, and vrefdq) must be at valid levels. the dram initiates a minimum of one refresh command internally within tcke period once it enters self - refresh mode. the clock is internally disabled during self - refresh operation to save pow er. the minimum time that the ddr3(l) sdram must remain in self - refresh mode is tcke. the user may change the external clock frequency or halt the external clock tcksre after self - refresh entry is registered; however, the clock must be restarted and stable tcksrx before the device can exit self - refresh mode. the procedure for exiting self - refresh requires a sequence of events. first, the clock must be stable prior to cke going back high. once a self - refresh exit command (srx, combination of cke going high and either nop or deselect on command bus) is registered, a delay of at least txs must be satisfied before a valid command not requiring a locked dll can be issued to the device to allow for any internal refresh in progress. before a command which requires a locked dll can be applied, a delay of at least txsdll and applicable zqcal function requirements must be satisfied. 9 x t r e f i t r e f i t t r e f i 8 r e f - c o m m a n d s p u l l e d - i n ddr3 (l) 2 gb sdram nt5c b( c ) 256 m8 f n / nt5cb(c) 128 m16 f p version 1. 6 6 4 nanya technology cooperation ? 0 4 / 201 4 all rights reserved. before a command that requires a locked dll can be applied, a delay of at least txsdll must be satisfied. depending on the system envi ronment and the amount of time spent in self - refresh, zq calibration commands may be required to compensate for the voltage and temperature drift as described in zq calibration commands. to issue zq calibration commands, applicable timing requirements mu st be satisfied. cke must remain high for the entire self - refresh exit period txsdll for proper operation except for self - refresh re - entry. upon exit from self - refresh, the ddr3(l) sdram can be put back into self - refresh mode after waiting at least txs pe riod and issuing one refresh command (refresh period of trfc). nop or deselect commands must be registered on each positive clock edge during the self - refresh exit interval txs. odt must be turned off during txsdll. the use of self - refresh mode instructs t he possibility that an internally times refresh event can be missed when cke is raised for exit from self - refresh mode. upon exit from self - refresh, the ddr3(l) sdram requires a minimum of one extra refresh com mand before it is put back into self - refresh mode. self - refresh entry/exit timing ck , ck t 1 t 2 ta 0 tb 0 tc 0 tc 1 te 0 tf odtl tcksre t c k s r x tcpded trf sre nop valid 2 ) tckesr txsdll txs cmd odt note : 1 . only nop or des commands 2 . valid commands not requiring a locked dll 3 . valid commands requiring a locked dll t 0 td 0 valid cke nop srx nop 1 ) valid 3 ) valid valid valid valid enter self refresh exit self refresh do not care time break ddr3 (l) 2 gb sdram nt5c b( c ) 256 m8 f n / nt5cb(c) 128 m16 f p version 1. 6 65 nanya technology cooperation ? 0 4 / 201 4 all rights reserved. power - down modes power - down entry and exit power - down is synchronously entered when cke is registered low (along with nop or deselect command). cke is not allowed to go low while mode register set command, mpr opera tions, zqcal operations, dll locking or read/write operation are in progress. cke is allowed to go low while any of other operation such as row activation, precharge or auto precharge and refresh are in progress, but power - down idd spec will not be applied until finishing those operation. the dll should be in a locked state when power - down is entered for fastest power - down exit timing. if the dll is not locked during power - down entry, the dll must be reset after exiting power - down mode for proper read opera tion and synchronous odt operation. dram design provides all ac and dc timing and voltage specification as well proper dll operation with any cke intensive operations as long as dram controller complies with dram specifications. during power - down, if all b anks are closed after any in progress commands are completed, the device will be in precharge power - down mode; if any bank is open after in progress commands are completed, the device will be in active power - down mode. entering power - down deactivates the input and output buffers, excluding ck, ck, odt, ??e , and re?et . to protect dram internal delay on cke line to block the input signals, multiple nop or deselect commands are needed during the cke switch off and cycle(s) after, this timing period are define d as tcpded. cke_low will result in deactivation of command and address receivers after tcpded has expired. power - down entry definitions status of dram mrs bit a12 dll pd exit relevant parameters active (a bank or more open) don't care on fast txp to any valid command. precharged (all banks precharged) 0 off slow txp to any valid command. since it is in precharge state, commands here will be act, ar, mrs/emrs, pr, or pra. txpdll to commands who need dll to operate, such as rd, rda, or odt control line. precharged (all banks precharged) 1 on fast txp to any valid command. also the dll is disabled upon entering precharge power - down (slow exit mode), but the dll is kept enabled during precharge power - down (fast exit mode) or active power - down. in power - dow n mode, cke low, re?et high, and a stable clock signal must be maintained at the inputs of the ddr3(l) sdram, and odt should be in a valid state but all other input signals are dont care (if re?et goes low during power - down, the dram will be out of pd mode and into rese t state). cke low must be maintain until tcke has been satisfied. power - down duration is limited by 9 times trefi of the device. ddr3 (l) 2 gb sdram nt5c b( c ) 256 m8 f n / nt5cb(c) 128 m16 f p version 1. 6 66 nanya technology cooperation ? 0 4 / 201 4 all rights reserved. the power - down state is synchronously exited when cke is registered high (along with a nop or deselect command). cke high must be maintained until tcke has been satisfied. a valid, executable command can be applied with power - down exit latency, txp and/or txpdll after cke goes high. power - down exit latency is defined at ac spec table of this datasheet. active power - down entry an d exit timing diagram t iming diagrams for cke with pd entry, pd exit with read, read with auto precharge, write and write with auto precharge, activ ate, precharge, refresh, mrs: power - down entry after read and read with auto precharge t 0 t 1 t 2 ta 0 ta 1 tb 0 tb 1 tc 0 ck ck valid nop nop nop nop nop nop cmd cke valid valid tis tih tpd tih tis tcke address valid valid tcpded enter power - down exit power - down txp do not care time break t 0 t 1 t a 0 t a 1 t a 2 t a 3 t a 4 t a 5 c k c k w r i t e n o p n o p n o p n o p n o p n o p c m d c k e a d d r e s s b a n k , c o l n p o w e r - d o w n e n t r y d o n o t c a r e t i m e b r e a k t a 6 t a 7 t b 0 t b 1 t b 2 n o p n o p n o p n o p n o p n o p t i s t c p d e d d q s w l = a l + c w l d i n b d i n b + 1 d i n b + 2 d i n b + 3 d i n b + 4 d i n b + 5 d i n b + 6 d i n b + 7 d i n b d i n b + 1 d i n b + 2 d i n b + 3 t w r a p d e n b l 8 b c 4 w r ( 1 ) t b 3 n o p t c 0 v a l i d t p d s t a r t i n t e r n a l p r e c h a r g e ddr3 (l) 2 gb sdram nt5c b( c ) 256 m8 f n / nt5cb(c) 128 m16 f p version 1. 6 67 nanya technology cooperation ? 0 4 / 201 4 all rights reserved. power - down entry after write with auto precharge t 0 t 1 t a 0 t a 1 t a 2 t a 3 t a 4 t a 5 c k c k r d o r r d a n o p n o p n o p n o p n o p n o p c m d c k e a d d r e s s v a l i d v a l i d p o w e r - d o w n e n t r y d o n o t c a r e t i m e b r e a k t a 6 t a 7 t a 8 t b 0 t b 1 n o p n o p n o p n o p n o p v a l i d v a l i d t i s t c p d e d d q s r l = a l + c l d i n b d i n b + 1 d i n b + 2 d i n b + 3 d i n b + 4 d i n b + 5 d i n b + 6 d i n b + 7 d i n b d i n b + 1 d i n b + 2 d i n b + 3 t r d p d e n b l 8 b c 4 t p d ddr3 (l) 2 gb sdram nt5c b( c ) 256 m8 f n / nt5cb(c) 128 m16 f p version 1. 6 68 nanya technology cooperation ? 0 4 / 201 4 all rights reserved. power - down entry after write precharge power - down (fast exit mode) entry and exit precharge power - down (slow exit mode) entry and exit t 0 t 1 t a 0 t a 1 t a 2 t a 3 t a 4 t a 5 c k c k w r i t e n o p n o p n o p n o p n o p n o p c m d c k e a d d r e s s b a n k , c o l n p o w e r - d o w n e n t r y d o n o t c a r e t i m e b r e a k t a 6 t a 7 t b 0 t b 1 t b 2 n o p n o p n o p n o p n o p n o p t i s t c p d e d d q s w l = a l + c w l d i n b d i n b + 1 d i n b + 2 d i n b + 3 d i n b + 4 d i n b + 5 d i n b + 6 d i n b + 7 d i n b d i n b + 1 d i n b + 2 d i n b + 3 t w r p d e n b l 8 b c 4 t c 0 n o p t p d w r t 0 t 1 t 2 t a 0 t a 1 t b 0 t b 1 t c 0 c k c k w r i t e n o p n o p n o p n o p n o p n o p c m d c k e d o n o t c a r e t i m e b r e a k n o p t i s t c p d e d t i h t c k e t i s t x p n o p v a l i d t p d e n t e r p o w e r - d o w n m o d e e x i t p o w e r - d o w n m o d e t 0 t 1 t 2 t a 0 t a 1 t b 0 t b 1 t c 0 c k c k w r i t e n o p n o p n o p n o p n o p v a l i d c m d c k e d o n o t c a r e t i m e b r e a k n o p t i s t c p d e d t i h t c k e t i s t x p n o p v a l i d t p d e n t e r p o w e r - d o w n m o d e e x i t p o w e r - d o w n m o d e t d 0 v a l i d t x p d l l v a l i d ddr3 (l) 2 gb sdram nt5c b( c ) 256 m8 f n / nt5cb(c) 128 m16 f p version 1. 6 69 nanya technology cooperation ? 0 4 / 201 4 all rights reserved. refresh command to power - down entry t 0 t 1 t 2 t 3 t a 0 t a 1 c k c k r e f n o p n o p v a l i d c m d c k e d o n o t c a r e t i m e b r e a k n o p t i s t c p d e d v a l i d t p d v a l i d v a l i d t r e f p d e n a d d r e s s ddr3 (l) 2 gb sdram nt5c b( c ) 256 m8 f n / nt5cb(c) 128 m16 f p version 1. 6 70 nanya technology cooperation ? 0 4 / 201 4 all rights reserved. active com mand to power - down entry precharge/precharge all command to power - down entry mrs command to power - down entry t 0 t 1 t 2 t 3 ta 0 ta 1 ck ck active nop nop valid cmd cke do not care time break nop tis tcpded valid tpd valid valid tactpden address t 0 t 1 t 2 t 3 ta 0 ta 1 ck ck pre prea nop nop valid cmd cke do not care time break nop tis tcpded valid tpd valid valid tprepden address t 0 t 1 ta 0 ta 1 tb 0 tb 1 ck ck nop nop valid cmd cke do not care time break nop tis tcpded valid tpd valid tmrspden address mrs valid ddr3 (l) 2 gb sdram nt5c b( c ) 256 m8 f n / nt5cb(c) 128 m16 f p version 1. 6 71 nanya technology cooperation ? 0 4 / 201 4 all rights reserved. on - die termination (odt) odt (on - die termination) is a feature of the ddr3(l) sdram that allows the dram to turn on/off termination resistance for each dq, dqs, ??? , and dm for x8 configuration and tdqs, t??? for x8 configuration, when enabled via a11=1 in mr1) via the odt control pin. the odt feature is designed to improve signal integrity of the memory channel by allowing the dram controller to independently tu rn on/off termination resistance for any or all dram devices. the odt feature is turned off and not supported in self - refresh mode. a simple functional representation of the dram odt feature is shown as below. functional representation of odt the sw itch is enabled by the internal odt control logic, which uses the external odt pin and other control information. the value of rtt is determined by the settings of mode register bits. the odt pin will be ignored if the mode register mr1 and mr2 are program med to disable odt and in self - refresh mode. odt mode register and odt truth table the odt mode is enabled if either of mr1 {a2, a6, a9} or mr2 {a9, a10} are non - zero. in this case, the value of rtt is determined by the settings of those bits. application : controller sends wr command together with odt asserted. one possible application: the rank that is being written to provides termination. dram turns on termination if it sees odt asserted (except odt is disabled by mr) dram does not use any write or read command decode information. termination truth table odt pin dram termination state 0 off 1 on, (off, if disabled by mr1 {a2, a6, a9} and mr2{a9, a10} in general) to other circuitry like rcv , ... vddq / 2 rtt switch dq , dqs , dm , tdqs odt ddr3 (l) 2 gb sdram nt5c b( c ) 256 m8 f n / nt5cb(c) 128 m16 f p version 1. 6 72 nanya technology cooperation ? 0 4 / 201 4 all rights reserved. synchronous odt mode synchronous odt mode is selected whenever the dll is turned on and locked. based on the power - down definition, these modes are: ? any bank active with cke high ? refresh with cke high ? idle mode with cke high ? active power down mode (regardless of mr0 bit a12) ? precharge power down mode if dll is enabled during precharge power d own by mr0 bit a12 the direct odt feature is not supported during dll - off mode. the on - die termination resistors must be disabled by continu - ously registering the odt pin low and/or by programming the rtt_nom bits mr1{a9,a6,a2} to {0,0,0} via a mode regist er set command during dll - off mode. in synchronous odt mode, rtt will be turned on odtlon clock cycles after odt is sampled high by a rising clock edge and turned off odtloff clock cycles after odt is registered low by a rising clock edge. the odt latency is tied to the write latency (wl) by: odtlonn = wl - 2; odtloff = wl - 2. odt latency and posted odt in synchronous odt mode, the additive latency (al) programmed into the mode register (mr1) also applies to the odt signal. the dram internal odt signal is d elayed for a number of clock cycles defined by the additive latency (al) relative to the external odt signal. odtlon = cwl + al - 2; odtloff = cwl + al - 2. for details, refer to ddr3(l) sdram latency definitions. odt latency symbol parameter ddr3 - 1600 un it odtlon odt turn on latency wl - 2 = cwl + al - 2 tck odtloff odt turn off latency wl - 2 = cwl + al - 2 tck ddr3 (l) 2 gb sdram nt5c b( c ) 256 m8 f n / nt5cb(c) 128 m16 f p version 1. 6 73 nanya technology cooperation ? 0 4 / 201 4 all rights reserved. timing parameters in synchronous odt mode, the following timing parameters apply: odtlon, odtloff , taon min/max, t aof min/max. minimum rtt tu rn - on time (t aon min) is the point in time when the device leaves high impedance and odt resistance begins to turn on. maximum rtt turn - on time (t aon max) is the point in time when the odt resistance is fully on. both are measured from odtlon. minimum rtt turn - off time (t aof min) is the point in time when the device starts to turn off the odt resistance. maximum rtt turn off time (t aof max) is the point in time when the on - die termination has reached high impedance. both are measured from odtloff. when odt is asserted, it must remain high until odth4 is satisfied. if a write command is registered by the sdram with odt high, then odt must remain high until odth4 (bl=4) or odth8 (bl=8) after the write command. odth4 and odth8 are measured from odt registered h igh to odt registered low or from the registration of a write command until odt is registered low. synchronous odt timing example for al=3; cwl=5; odtlon=al+cwl - 2=6; odtloff=al+cwl - 2=6 synchronous odt example with bl=4, wl=7 odt must be held for at leas t odth4 after assertion (t1); odt must be kept high odth4 (bl=4) or odth8 (bl=8) after write command (t7). odth is measured from odt first registered high to odt first registered low, or from registration of write command with odt high to odt registered lo w. note that although odth4 is satisfied from odt registered at t6 odt must not go low before t11 as odth4 must also be satisfied from the registration of the write command at t7. ck ck al = 3 t 11 t 10 t 0 t 1 t 3 t 5 t 6 t 7 t 9 t 2 t 4 t 8 t 12 odt odth 4 , min odtlon = cwl + al - 2 odtloff = cwl + al - 2 t 13 t 14 t 15 cwl - 2 dram _ rtt taonmin taonmax taonmin taonmax rtt _ nom al = 3 transitioning do not care cke ck ck odth 4 t 11 t 10 t 0 t 1 t 3 t 5 t 6 t 7 t 9 t 2 t 4 t 8 t 12 odt odtlon = cwl - 2 t 13 t 14 t 15 odtloff = wl - 2 dram _ rtt taonmin taonmax taofmax rtt _ nom t 16 t 17 t 18 odth 4 min odth 4 odtloff = cwl - 2 odtlon = cwl - 2 taofmin taofmax taonmax taonmin taofmin nop nop nop nop nop nop nop wrs 4 nop nop nop nop nop nop nop nop nop nop nop transitioning do not care ddr3 (l) 2 gb sdram nt5c b( c ) 256 m8 f n / nt5cb(c) 128 m16 f p version 1. 6 74 nanya technology cooperation ? 0 4 / 201 4 all rights reserved. odt during reads: as the ddr3(l) sdram cannot terminate and drive at the sam e time, rtt must be disabled at least half a clock cycle before the read preamble by driving the odt pin low appropriately. rtt may not be enabled until the end of the post - amble as shown in the following figure. dram turns on the termination when it stops driving which is determined by thz. if dram stops driving early (i.e. thz is early), then taonmin time may apply. if dram stops driving late (i.e. thz is late), then dra m complies with taonmax timing. note that odt may be disabled earlier before the read and enabled later after the read than shown in this example. odt must be disabled externally during reads by driving odt low. (example: cl=6; al=cl - 1=5; rl=al+cl=11; cwl=5; odtlon=cwl+al - 2=8; odtloff=cwl+al - 2=8) ck ck t 11 t 10 t 0 t 1 t 3 t 5 t 6 t 7 t 9 t 2 t 4 t 8 t 12 t 13 t 14 t 15 t 16 cmd address rl = al + cl rtt _ nom rtt odtloff = cwl + al - 2 taofmax taofmin odtlon = cwl + al - 2 rtt _ nom taonmax odt dram odt dqsdiff din b din b + 1 din b + 2 din b + 3 din b + 4 din b + 5 din b + 6 din b + 7 dq read nop nop nop nop nop nop nop nop nop nop nop nop nop nop nop nop valid ddr3 (l) 2 gb sdram nt5c b( c ) 256 m8 f n / nt5cb(c) 128 m16 f p version 1. 6 75 nanya technology cooperation ? 0 4 / 201 4 all rights reserved. dynamic odt in certain application cases and to further enhance signal integrity on the data bus, it is desirable that the termination strength of the ddr3(l) sdram can be changed without issuing an mrs command. this requirement is supported by the dynamic odt feature as described as follows: functional description the dynamic odt mode is enabled if bit (a9) or (a10) of mr2 is set to 1. the function is described as follows: two rtt values are available: rtt_nom and rtt_wr. ? the value for rtt_nom is preselected via bits a[9,6,2] in mr1. ? the val ue for rtt_wr is preselected via bits a[10,9] in mr2. during operation without write commands, the termination is controlled as follows: ? nominal termination strength rtt_nom is selected. ? termination on/off timing is controlled via odt pin and latencies odt lon and odtloff. when a write command (wr, wra, wrs4, wrs8, wras4, wras8) is registered, and if dynamic odt is enabled, the termi nation is controlled as follows: ? a latency odtlcnw after the write command, termination strength rtt_wr is selected. ? a latency odtlcwn8 (for bl8, fixed by mrs or selected otf) or odtlcwn4 (for bc4, fixed by mrs or selected otf) after the write command, termination strength rtt_nom is selected. ? termination on/off timing is controlled via odt pin and odtlon, odtloff. the following table shows latencies and timing parameters which are relevant for the on - die termination control in dynamic odt mode. the dynamic odt feature is not supported at dll - off mode. user must use mrs command to set rtt_wr, mr2[a10,a9 = [0,0], to disable dynami c odt externally. when odt is asserted, it must remain high until odth4 is satisfied. if a write command is registered by the sdram with odt high, then odt must remain high until odth4 (bl=4) or odth8 (bl=8) after the write command. odth4 and odth8 are mea sured from odt registered high to odt registered low or from the registration of write command until odt is register low. ddr3 (l) 2 gb sdram nt5c b( c ) 256 m8 f n / nt5cb(c) 128 m16 f p version 1. 6 76 nanya technology cooperation ? 0 4 / 201 4 all rights reserved. latencies and timing parameters relevant for dynamic odt name and description abbr. defined from defined to definition for all ddr3(l ) speed pin unit odt turn - on latency odtlon registering external odt signal high turning termination on odtlon=wl - 2 tck odt turn - off latency odtloff registering external odt signal low turning termination off odtloff=wl - 2 tck odt latency for changing fr om rtt_nom to rtt_wr odtlcnw registering external write command change rtt strength from rtt_nom to rtt_wr odtlcnw=wl - 2 tck odt latency for change from rtt_wr to rtt_nom (bl=4) odtlcwn4 registering external write command change rtt strength from rtt_w r to rtt_nom odtlcwn4=4+odtloff tck odt latency for change from rtt_wr to rtt_nom (bl=8) odtlcwn8 registering external write command change rtt strength from rtt_wr to rtt_nom odtlcwn8=6+odtloff tck(avg) minimum odt high time after odt assertion odth 4 registering odt high odt registered low odth4=4 tck(avg) minimum odt high time after write (bl=4) odth4 registering write with odt high odt registered low odth4=4 tck(avg) minimum odt high time after write (bl=8) odth8 registering write with odt high odt register low odth8=6 tck(avg) rtt change skew tadc odtlcnw odtlcwn rtt valid tadc(min)=0.3tck(avg) tadc(max)=0.7tck(avg) tck(avg) note: taof,nom and tadc,nom are 0.5tck (effectively adding half a clock cycle to odtloff, odtcnw, and odtlcwn) ddr3 (l) 2 gb sdram nt5c b( c ) 256 m8 f n / nt5cb(c) 128 m16 f p version 1. 6 77 nanya technology cooperation ? 0 4 / 201 4 all rights reserved. odt t iming diagrams dynamic odt: behavior with odt being asserted before and after the write note: example for bc4 (via mrs or otf), al=0, cwl=5. odth4 applies to first registering odt high and to the registration of t he write command. in this example odth4 wo uld be satisfied if odt went low at t8. (4 clocks after the write command). dynamic odt: behavior without write command, al=0, cwl=5 note: odth4 is defined from odt registered high to odt registered low, so in this example odth4 is satisfied; odt regis t ered low at t5 would also be legal. ck ck t 11 t 10 t 0 t 1 t 3 t 5 t 6 t 7 t 9 t 2 t 4 t 8 t 12 t 13 t 14 t 15 t 16 cmd odt rtt dqs / dqs dq odtlon odtlcwn 4 t 17 odtlcnw taonmin taonmax tadcmin tadcmax wl tadcmin tadcmax taofmin taofmax address rtt _ wr din n din n + 1 din n + 2 din n + 3 odth 4 odtloff nop nop nop nop wrs 4 nop nop nop nop nop nop nop nop nop nop nop nop nop valid odth 4 rtt _ nom do not care transitioning rtt _ nom tadcmax ck ck t 11 t 10 t 0 t 1 t 3 t 5 t 6 t 7 t 9 t 2 t 4 t 8 cmd odt rtt dqs / dqs dq odtlon odtloff taonmin taonmax tadcmin rtt _ nom valid valid valid valid valid valid valid valid valid valid valid valid address odth 4 odtloff do not care transitioning ddr3 (l) 2 gb sdram nt5c b( c ) 256 m8 f n / nt5cb(c) 128 m16 f p version 1. 6 78 nanya technology cooperation ? 0 4 / 201 4 all rights reserved. dynamic odt: behavior with odt pin being asserted together with write command for the duration of 6 clock cycles. note: example for bl8 (via mrs or otf), al=0, cwl=5. in this example odth8=6 is exactly satisfied. dynam ic odt: behavior with odt pin being asserted together with write command for a duration of 6 clock cycles, example for bc4 (via mrs or otf), al=0, cwl=5. taofmax taofmin ck ck t 11 t 10 t 0 t 1 t 3 t 5 t 6 t 7 t 9 t 2 t 4 t 8 cmd odt rtt dqs / dqs dq odth 8 odtlon odtlcnw taonmin taonmax odtloff wl rtt _ wr nop wrs 8 nop nop nop nop nop nop nop nop nop nop valid din h din h + 1 din h + 2 din h + 3 din h + 4 din h + 5 din h + 6 din h + 7 odtlcwn 8 do not care transitioning address ck ck t 11 t 10 t 0 t 1 t 3 t 5 t 6 t 7 t 9 t 2 t 4 t 8 odt rtt dqs / dqs dq odtlon rtt _ wr rtt _ nom odtlcnw taonmin tadcmin tadcmax taofmin taofmax taonmax odtloff wl odth 4 odtlcwn 4 cmd nop wrs 4 nop nop nop nop nop nop nop nop nop nop valid address din n din n + 1 din n + 2 din n + 3 do not care transitioning ddr3 (l) 2 gb sdram nt5c b( c ) 256 m8 f n / nt5cb(c) 128 m16 f p version 1. 6 79 nanya technology cooperation ? 0 4 / 201 4 all rights reserved. dynamic odt: behavior with odt pin being asserted together with write command for the duration of 4 clock cycles. ck ck # t 11 t 10 t 0 t 1 t 3 t 5 t 6 t 7 t 9 t 2 t 4 t 8 odt rtt dqs / dqs dq odtlon rtt _ wr odtlcnw taonmin taofmin taofmax taonmax odtloff wl odth 4 odtlcwn 4 cmd nop wrs 4 nop nop nop nop nop nop nop nop nop nop valid address din n din n + 1 din n + 2 din n + 3 do not care transitioning ddr3 (l) 2 gb sdram nt5c b( c ) 256 m8 f n / nt5cb(c) 128 m16 f p version 1. 6 80 nanya technology cooperation ? 0 4 / 201 4 all rights reserved. asynchronous odt mode asynchronous odt mode is selected when dram runs in dllon mode, but dll is temporaril y disabled (i.e. frozen) in pre charge power - down (by mr0 bit a12). based on the power down mode definitions, this is currently prechar ge power down mode if dll is disabled during precharge power down by mr0 bit a12. in asynchronous odt timing mode, internal odt command is not delayed by additive latency (al) relative to the external odt command. in asynchronous odt mode, the following t iming parameters apply: t aonpd min/max, t aofpd min/max. minimum rtt turn - on time (t aonpd min) is the point in time when the device termination circuit leaves high impedance state and odt resistance begins to turn on. maximum rtt turn on time (t aonpd max) is the point in time when the odt resistance is fully on. t aonpd min and t aonpd max are measured from odt being sampled high. minimum rtt turn - off time (t aofpd min) is the point in time when the devices termination circuit starts to turn off the odt resistanc e. maximum odt turn off time (t aofpd max) is the point in time when the on - die termination has reached high impedance. t aofpd min and t aofpd max are measured from odt being sample low. asynchronous odt timings on ddr3(l) sdram with fast odt transition: al is ignored. in precharge power down, odt receiver remains active; however no read or write command can be issued, as the respective add/cmd receivers may be disabled. asynchronous odt timing parameters for all speed bins symbol description min . max . unit t aonpd asynchronous rtt turn - on delay (power - down with dll frozen) 2 8.5 ns t aofpd asynchronous rtt turn - off delay (power - down with dll frozen) 2 8.5 ns ck ck # t 11 t 10 t 0 t 1 t 3 t 5 t 6 t 7 t 9 t 2 t 4 t 8 odt rtt taonpdmin cke tih tis t 12 t 13 t 14 t 15 taonpdmax taofpdmin taofpdmax tih tis do not care transitioning ddr3 (l) 2 gb sdram nt5c b( c ) 256 m8 f n / nt5cb(c) 128 m16 f p version 1. 6 81 nanya technology cooperation ? 0 4 / 201 4 all rights reserved. odt timing parameters for power down (with dll frozen) entry and exit transition period description min . max . odt to rtt turn - on delay min{ odtlon * tck + taonmin; taonpdmin } min{ (wl - 2) * tck + taonmin; taonpdmin } max{ odtlon * tck + taonmax; taonpdmax } max{ (wl - 2) * tck + taonmax; taonpfmax } odt to rtt turn - off delay min{ odtloff * tck + taof min; taofpdmin } min{ (wl - 2) * tck + taofmin; taofpdmin } max{ odtloff * tck + taofmax; taofpdmax } max{ (wl - 2) * tck + taofmax; taofpdmax } tanpd wl - 1 synchronous to asynchronous odt mode transition during power - down entry if dll is selected to be frozen in precharge power down mode by the setting of bit a12 in mr0 to 0, there is a transition period around power down entry, where the ddr3(l) sdram may show either synchronous or asynchronous odt behavior. the transition period is defined by the par ameters tanpd and tcpded(min). tanpd is equal to (wl - 1) and is counted backwards in time from the clock cycle where cke is first registered low. tcpded(min) starts with the clock cycle where cke is first registered low. the transition period begins with th e starting point of tanpd and terminates at the end point of tcpded(min). if there is a refresh command in progress while cke goes low, then the transition period ends at the later one of trfc(min) after the refresh command and the end point of tcpded(min) . please note that the actual starting point at tanpd is excluded from the transition period, and the actual end point at tcpded(min) and trfc(min, respectively, are included in the transition period. odt assertion during the transition period may result i n an rtt change as early as the smaller of taonpdmin and (odtlon*tck + taonmin) and as late as the larger of taonpdmax and (odtlon*tck + taonmax). odt de - assertion during the transition period may result in an rtt change as early as the smaller of taofpdmi n and (odtloff*tck + taofmin) and as late as the larger of taofpdmax and (odtloff*tck + taofmax). note that, if al has a large value, the range where rtt is uncertain becomes quite large. figure 85 shows the three different cases: odt_a, synchronous behavi or before tanpd; odt_b has a state change during the transition period; odt_c shows a state change after the transition period. ddr3 (l) 2 gb sdram nt5c b( c ) 256 m8 f n / nt5cb(c) 128 m16 f p version 1. 6 82 nanya technology cooperation ? 0 4 / 201 4 all rights reserved. synchronous to asynchronous transition during precharge power down (with dll frozen) entry (al=0; cwl=5; tanpd=wl - 1=4) ck ck cke cmd last sync . odt tanpd rtt sync . or async . odt odtloff taofmax taofmin taofpdmin taofpdmax odtloff + taofpdmin odtloff + taofpdmax rtt taofpdmin first async . odt rtt nop nop nop nop nop nop nop nop nop nop nop nop t 1 t 2 t 3 t 4 t 5 t 6 t 7 t 8 t 9 t 10 t 11 t 12 pd entry transition period do not care time break transitioning tcpdedmin tcpded nop rtt rtt rtt taofpdmax ddr3 (l) 2 gb sdram nt5c b( c ) 256 m8 f n / nt5cb(c) 128 m16 f p version 1. 6 83 nanya technology cooperation ? 0 4 / 201 4 all rights reserved. asynchro nous to synchronous odt mode transition during power - down exit if dll is selected to be frozen in precharge power down mode by the setting of bit a12 in mr0 to 0, there is also a transition period around power down exit, where either synchronous or async hronous response to a change in odt must be expected from the ddr3(l) sdram. this transition period starts tanpd before cke is first registered high, and ends txpdll after cke is first registered high. t anpd is equal to (wl - 1) and is counted (backwards) f rom the clock cycle where cke is first registered high. odt assertion during the transition period may result in an rtt change as early as the smaller of t aonpd min and (odt - lon*tck+t aon min) and as late as the larger of t aonpd max and (odtlon*tck+t aon max). o dt de - assertion during the tran - sition period may result in an rtt change as early as the smaller of t aofpd min and (odtloff*tck+t aof min) and as late as the larger of t aofpd max and (odtoff*tck+t aof max). note that if al has a large value, the range where rtt is uncertain becomes quite large. the following figure shows the three different cases: odt_c, asynchronous response before t anpd ; odt_b has a state change of odt during the transition period; odt_a shows a state change of odt after the transition period with synchronous response. asynchronous to synchronous transition during precharge power down (with dll frozen) exit (cl=6; al=cl - 1; cwl=5; tanpd=wl - 1=9) ck ck odt _ c _ sync dram _ rtt _ c _ sync odt _ b _ tran taofpdmax taofpdmin dram _ rtt _ b _ tran odt _ a _ async dram _ rtt _ a _ async t 0 t 1 t 2 ta 0 ta 1 ta 2 ta 3 ta 4 ta 5 ta 6 tb 0 tb 1 tb 2 tc 0 tc 1 tc 2 td 0 do not care time break transitioning td 1 cmd nop nop nop nop nop nop nop nop nop nop nop nop cke nop txpdll pd exit transition period rtt rtt taofpdmin odtloff + taofmax odtloff + taofmin taofpdmax tanpd nop taofmax rtt odtloff taofmin ddr3 (l) 2 gb sdram nt5c b( c ) 256 m8 f n / nt5cb(c) 128 m16 f p version 1. 6 84 nanya technology cooperation ? 0 4 / 201 4 all rights reserved. asynchronous to synchronous odt mode during short cke high and short cke low periods if the total t ime in precharge power down state or idle state is very short, the transition periods for pd entry and pd exit may overlap. in this case, the response of the ddr3(l) sdrams rtt to a change in odt state at the input may be synchronous or asynchronous from t he state of the pd entry transition period to the end of the pd exit transition period (even if the entry ends later than the exit period). if the total time in idle state is very short, the transition periods for pd exit and pd entry may overlap. in this case, the response of the ddr3(l) sdrams rtt to a change in odt state at the input may be synchronous or asynchronous from the state of the pd exit transition period to the end of the pd entry transition period. note that in the following figure, i t is ass umed that there was no refresh command in progress when idle state was entered. transition period for short cke cycles with entry and exit period overlapping (al=0; wl=5; tanpd=wl - 1=4) ck ck t 11 t 10 t 0 t 1 t 3 t 5 t 6 t 7 t 9 t 2 t 4 t 8 t 12 t 13 t 14 tanpd do not care transitioning cke cmd ref nop nop nop nop nop nop nop nop nop nop nop nop nop nop pd exit transition period tanpd txpdll pd entry transition period trfc ( min ) cke short cke high transition period txpdll ddr3 (l) 2 gb sdram nt5c b( c ) 256 m8 f n / nt5cb(c) 128 m16 f p version 1. 6 85 nanya technology cooperation ? 0 4 / 201 4 all rights reserved. zq calibration commands zq calibration description zq calibration co mmand is used to calibrate dram ron and odt values. ddr3(l) sdram needs longer time to calibrate output driver and on - die termination circuits at initialization and relatively smaller time to perform periodic calibrations. zqcl command is used to perform t he initial calibration during power - up initialization sequence. this command may be issued at any time by the controller depending on the system environment. zqcl command triggers the calibration engine inside the dram and once calibration is achieved the calibrated values are transferred from calibration engine to dram io which gets reflected as updated output driver and on - die termination values. the first zqcl command issued after reset is allowed a timing period of tzqinit to perform the full calibratio n and the transfer of values. all other zqcl commands except the first zqcl command issued after reset is allowed a timing period of tzqoper. zqcs command is used to perform periodic calibrations to account for voltage and temperature variations. a shorter timing win dow is provided to perform the calibration and transfer of values as defined by timing parameter tzqcs. no other activities should be performed on the dram channel by the controller for the duration of tzqinit, tzqoper, or tzqcs. the quiet time on the dram channel allows calibration of output driver and on - die termination values. once dram calibration is achieved, the dram should disable zq current consumption path to reduce power. all banks must be precharged and trp met before zqcl or zqcs com mands are issued by the controller. zq calibration commands can also be issued in parallel to dll lock time when coming out of self refresh. upon self - refresh exit, ddr3(l) sdram will not perform an io calibration without an explicit zq calibration comman d. the earliest possible time for zq calibration command (short or long) after self refresh exit is txs. in systems that share the zq resistor between devices, the controller must not allow any overlap of tzqoper, tzqinit, or tzqcs between ranks. ddr3 (l) 2 gb sdram nt5c b( c ) 256 m8 f n / nt5cb(c) 128 m16 f p version 1. 6 86 nanya technology cooperation ? 0 4 / 201 4 all rights reserved. zq cali bration timing note: 1. cke must be continuously registered high during the calibration procedure. 2. on - die termination must be disabled via the odt signal or mrs during the calibration procedure. 3. all devices connected to the dq bus should be high impedance dur ing the calibration procedure. zq external resistor value, tolerance, and capacitive loading in order to use the zq calibration function, a 240 ohm +/ - 1% tolerance external resistor connected between the zq pin and ground. the single resistor can be used for each sdram or one resistor can be shared between two sdrams if the zq calibration timings for each sdram do not overlap. the total capacitive loading on the zq pin must be limited. ck ck tc 2 t 0 t 1 ta 1 ta 3 tb 0 tb 1 tc 1 ta 0 ta 2 tc 0 address cmd zqcl nop nop nop valid valid zqcs nop nop nop valid odt tzqcs valid valid valid valid valid a 10 cke valid valid valid valid valid valid ( 1 ) ( 2 ) ( 1 ) ( 2 ) dq bus hi - z activities hi - z activities tzqcs ( 3 ) ( 3 ) do not care time break ddr3 (l) 2 gb sdram nt5c b( c ) 256 m8 f n / nt5cb(c) 128 m16 f p version 1. 6 87 nanya technology cooperation ? 0 4 / 201 4 all rights reserved. absolute maximum ratings absolute maximum dc ratings symbol parameter rating unit note vdd voltage on vdd pin relative to vss - 0.4 v ~ 1.80 v v 1,3 vddq voltage on vddq pin relative to vss - 0.4 v ~ 1.80 v v 1,3 vin, vout voltage on any pin relative to vss - 0.4 v ~ 1.80 v v 1 tstg storage temperature - 55 ~ 100 ? c 1,2 not e: 1. stresses greater than those listed under "absolute maximum ratings" may cause permanent damage to the device.this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational s ections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. storage temperature is the case surface temperature on the center/top side of the dram. 3. vdd and vddq must be within 3 00mv of each other at all times; and vref must be not greater than 0.6vddq, when vdd and vddq are less than 500mv; vref may be equal to or less than 300mv. refresh paramet ers by device density parameter symbol 1gb 2gb 4gb 8gb unit ref command to act or ref command time trfc 110 160 260 350 ns ddr3 (l) 2 gb sdram nt5c b( c ) 256 m8 f n / nt5cb(c) 128 m16 f p version 1. 6 88 nanya technology cooperation ? 0 4 / 201 4 all rights reserved. temperature range symbol condition parameter value unit notes toper commercial normal operating temperature range 0 to 85 ? c 1,2 extended temperature range 85 to 95 ? c 1,3 industrial operating temperature range - 40 to 95 ? c 1.4 automotive grade 2 operating temperature range - 40 to 105 ? c 1 automotive grade 3 operating temperature range - 40 to 9 5 ? c 1.4 note: 1. operating temperature toper is the case surface temperature on the center/top side of the d ram. 2. the n ormal temperature range specifies the temperatures where all dram specification will be supported. during operation, the dram case temperature must be maintained between 0 - 85 ? c under all operating conditions. 3. some applications require ope ration of the dram in the extended temperature range between 85 ? c and 95 ? c case temperature. full specifications are guaranteed in this range, but the following additional apply . a) refresh commands must be doubled in frequency, therefore, reducing the refr esh interval trefi to 3.9us. it is also possible to specify a component with 1x refresh (trefi to 7.8us) in the extended temperature range. b) if self - refresh operation is required in the extended temperature range, then it is mandatory to either use the ma nual self - refresh mode with extended temperature range capability (mr2 a6=0 and mr2 a7=1) or enable the optional auto self - refresh mode (mr2 a6=1 and mr2 a7=0). 4. during temperature o peration range , the dram case temperature must be maintained between - 40 c~95 c under all operating conditions . ddr3 (l) 2 gb sdram nt5c b( c ) 256 m8 f n / nt5cb(c) 128 m16 f p version 1. 6 89 nanya technology cooperation ? 0 4 / 201 4 all rights reserved. ac & dc operating conditions recommended dc operating conditions symbol parameter rating unit note min. typ. max. vdd supply voltage ddr3 1.425 1.5 1.575 v 1,2 ddr3l 1.283 1.35 1.45 3,4,5,6 vddq supply v oltage for output ddr3 1.425 1.5 1.575 v 1,2 ddr3l 1.283 1.35 1.45 3,4,5,6 note: 1. under all conditions vddq must be less than or equal to vdd. 2. vddq tracks with vdd. ac parameters are measured with vdd and vddq tied together. 3 . maximun dc value m ay not be great than 1.425v. the dc value is the linear average of vdd/ vddq(t) over a very long period of time (e.g., 1 sec). 4. if maximum limit is exceeded, input levels shall be governed by ddr3 specifications. 5. under these supply voltages, the devi ce operates to this ddr3l specification. 6 . once initialized for ddr3 operation, ddr3l operation may only be used if the device is in reset while vdd and vddq are chan ged for ddr3l operation. 7. vdd= vddq= 1.35v (1.283 C 1.45v ) backward compatible to vdd= vddq= 1.5v 0.075v supports ddr3l devices to be backward com - patible in 1.5v applications ddr3 (l) 2 gb sdram nt5c b( c ) 256 m8 f n / nt5cb(c) 128 m16 f p version 1. 6 90 nanya technology cooperation ? 0 4 / 201 4 all rights reserved. ac & dc input measurement levels ddr3 ac and dc logic input levels for command and address symbol parameter ddr3 unit notes 800 , 1066 ,1 333 ,1 600 1866 , 2133 min max min max vih.ca(dc100) dc input logic high vref + 0.1 vdd vref + 0.1 vdd v 1, 5 vil.ca(dc100) dc input logic low vss vref - 0.1 vss vref - 0.1 v 1, 6 vih.ca(ac175) ac input logic high vref + 0.175 note 2 - - v 1, 2, 7 vil.ca(ac175) ac input logic low note 2 vref - 0.175 - - v 1, 2, 8 vih.ca(ac150) ac input logic high vref + 0.150 note 2 - - v 1, 2, 7 vil.ca(ac150) ac input logic low note 2 vref - 0.150 - - v 1, 2, 8 vih.ca(ac135) ac input logic high - - vref + 0.135 note 2 v 1, 2, 7 vil.ca(ac13 5) ac input logic low - - note 2 vref - 0.135 v 1, 2, 8 vih.ca(ac125) ac input logic high - - - note 2 v 1, 2, 7 vil.ca(ac125) ac input logic low - - note 2 vref - 0.125 v 1, 2, 8 vrefca(dc) reference voltage for add, cmd inputs 0.49 * vdd 0.51 * vdd 0. 49 * vdd 0.51 * vdd v 3, 4, 9 note 1. for input only pins except re?et . vref = vrefca(dc). note 2. see overshoot and undershoot specifications . note 3. the ac peak noise on vref may not allow vref to deviate from vrefca(dc) by more than +/ - 1% vdd (for reference: approx. +/ - 15 mv). note 4. for reference: approx. vdd/2 +/ - 15 mv. note 5. vih(dc) is used as a simplified symbol for vih.ca(dc100) note 6. vil(dc) is used as a simplified symbol for vil.ca(dc100) note 7. vih(ac) is used as a simplified symbol for vih.ca(ac175), vih.ca(ac150), vih.ca(ac135), and vih.ca(ac125); vih.ca(ac175) value is used when vref + 0.175v is referenced, vih.ca(ac150) value is used when vref + 0.150v is referenced, vih.ca(ac135) v alue is used when vref + 0.135v is referenced, an d vih.ca(ac125) value is used when vref + 0.125v is referenced. note 8. vil(ac) is used as a simplified symbol for vil.ca(ac175), vil.ca(ac150), vil.ca(ac135) and vil.ca(ac125); vil.ca(ac17 5) value is used when vref - 0.175v is referenced, vil.ca(ac150) va lue is used when vref - 0.150v is referenced, vil.ca(ac135) value is used when vref - 0.135v is referenced, and vil.ca(ac125) value is used when vref - 0.125v is referenced. note 9. vrefca(dc) is measured relative to vdd at the same point in time on the sa me device ddr3 (l) 2 gb sdram nt5c b( c ) 256 m8 f n / nt5cb(c) 128 m16 f p version 1. 6 91 nanya technology cooperation ? 0 4 / 201 4 all rights reserved. ddr3l ac and dc logic input levels for command and address symbol parameter ddr3l unit notes 800, 1066 1333, 1600 1866 min max min max min max vih.ca (dc90) dc input logic high vref + 0.09 v dd vref + 0.09 v dd vref + 0.09 v dd v 1 vil. ca (dc90) dc input logic low v ss vref - 0.09 v ss vref - 0.09 v ss vref - 0.09 v 1 vih.ca (ac160) ac input logic high vref + 0.16 note 2 vref + 0.16 note 2 - - v 1,2 vil.ca (ac160) ac input logic low note 2 vref - 0.16 note 2 vref - 0.16 - - v 1,2 vih.ca (ac1 35) ac input logic high vref + 0.135 note 2 vref + 0.135 note 2 vref + 0.135 note 2 v 1,2 vil.ca (ac135) ac input logic low note 2 vref - 0 .135 note 2 vref - 0 .135 note 2 vref - 0 .135 v 1,2 vih.ca (ac125) ac input logic high - - - - vref + 0.125 note 2 v 1 ,2 vil.ca (ac125) ac input logic low - - - - note 2 vref - 0.125 v 1,2 vrefca (dc) reference voltage for add, cmd inputs 0.49 * v dd 0.51 * v dd 0.49 * v dd 0.51 * v dd 0.49 * v dd 0.51 * v dd v 3,4 note 1 for input only pins except re?et . vref = vrefca(dc). note 2 see overshoot and undershoot specifications note 3 the ac peak noise on vref may not allow vref to deviate from vrefdq(dc) by more than +/ - 1% vdd (for reference: approx. +/ - 13.5 mv). note 4 for reference: approx. vdd/2 + / - 13.5 mv ddr3 (l) 2 gb sdram nt5c b( c ) 256 m8 f n / nt5cb(c) 128 m16 f p version 1. 6 92 nanya technology cooperation ? 0 4 / 201 4 all rights reserved. ddr3 ac and dc logic input levels for dq and dm symbol parameter ddr3 unit notes 800, 1066 1333, 1600 1866, 2133 min max min max min max vih.dq(dc100) dc input logic high vref + 0.1 vdd vref + 0.1 vdd vref + 0.1 vdd v 1, 5 vil.dq(dc 100) dc input logic low vss vref - 0.1 vss vref - 0.1 vss vref - 0.1 v 1, 6 vih.dq(ac175) ac input logic high vref + 0.175 note 2 - - - - v 1, 2, 7 vil.dq(ac175) ac input logic low note 2 vref - 0.175 - - - - v 1, 2, 8 vih.dq(ac150) ac input logic high vref + 0.150 note 2 vref + 0.150 note 2 - - v 1, 2, 7 vil.dq(ac150) ac input logic low note 2 vref - 0.150 note 2 vref - 0.150 - - v 1, 2, 8 vih.dq(ac135) ac input logic high vref + 0.135 note 2 vref + 0.135 note 2 vref + 0.135 note 2 v 1, 2, 7 vil.dq(a c135) ac input logic low note 2 vref - 0.135 note 2 vref - 0.135 note 2 vref - 0.135 v 1, 2, 8 vref dq (dc) reference voltage for dq , dm inputs 0.49 * vdd 0.51 * vdd 0.49 * vdd 0.51 * vdd 0.49 * vdd 0.51 * vdd v 3, 4, 9 note 1. vref = vrefdq(dc). note 2. s ee overshoot and undershoot specifications . note 3. the ac peak noise on vref may not allow vref to deviate from vrefdq(dc) by more than +/ - 1% vdd (for reference:approx. +/ - 15 mv). note 4. for reference: approx. vdd/2 +/ - 15 mv. note 5. vih(dc) is used as a simplified symbol for vih.dq(dc100) note 6. vil(dc) is used as a simplified symbol for vil.dq(dc100) note 7. vih(ac) is used as a simplified symbol for vih.dq(ac175), vih.dq(ac150), and vih.dq(ac135);vih.dq(ac175) value is use d when vref + 0.175v is referenced, vih.dq(ac150) value is used when vref + 0.150v is referenced, and vih.dq(ac135) value is used when vref + 0.135v is referenced. note 8. vil(ac) is used as a simplified symbol for vil.dq(ac175), vil.dq(ac150), and vil.dq(ac135);vil.dq(ac175) val ue is used when vref - 0.175v is referenced, vil.dq(ac150) value is used when vref - 0.150v is referenced, and vil.dq(ac135) value is used when vref - 0.135v is referenced. note 9. vrefca(dc) is measured relative to vdd at the same point in time on the same device ddr3 (l) 2 gb sdram nt5c b( c ) 256 m8 f n / nt5cb(c) 128 m16 f p version 1. 6 93 nanya technology cooperation ? 0 4 / 201 4 all rights reserved. ddr3l ac and dc logic input levels for dq and dm symbol parameter ddr3l unit notes 800,1066 1333,1600 1866 min max min max min max vih. dq (dc90) dc input logic high vref + 0.09 v dd vref + 0.09 v dd vref + 0.09 v dd v 1 vil. dq (dc90) dc i nput logic low v ss vref - 0.09 v ss vref - 0.09 v ss vref - 0.09 v 1 vih. dq (ac160) ac input logic high vref + 0.16 note 2 vref + 0.16 note 2 - - v 1,2 vil. dq (ac160) ac input logic low note 2 vref - 0.16 note 2 vref - 0.16 - - v 1,2 vih. dq (ac135) ac input logic high vref + 0.135 note 2 vref + 0.135 note 2 vref + 0.135 note 2 v 1,2 vil. dq (ac135) ac input logic low note 2 vref - 0 .135 note 2 vref - 0 .135 note 2 vref - 0 .135 v 1,2 vih. dq (ac1 30 ) ac input logic high - - - - vref + 0.1 3 note 2 v 1,2 vil. dq (ac1 30 ) ac input logic low - - - - note 2 vref - 0.1 3 v 1,2 vref dq (dc) reference voltage for dq , dm inputs 0.49 * v dd 0.51 * v dd 0.49 * v dd 0.51 * v dd 0.49 * v dd 0.51 * v dd v 3,4 note 1 for input only pins except re?et . vref = vrefdq(dc). note 2 see overshoot and undershoot specifications . note 3 the ac peak noise on vref may not allow vref to deviate from vrefdq(dc) by more than +/ - 1% vdd (for reference: approx. +/ - 13.5 mv ). note 4 for reference: approx. vdd /2 +/ - 13.5 mv . ddr3 (l) 2 gb sdram nt5c b( c ) 256 m8 f n / nt5cb(c) 128 m16 f p version 1. 6 94 nanya technology cooperation ? 0 4 / 201 4 all rights reserved. vref tolerances the dc - tolerance limits and ac - moist limits for the reference voltages vrefca and vrefdq are illustrated in the following figure. it shows a valid reference voltage vref(t) as a function of time. (vref stands for vrefca and vrefdq likewise). vref(dc) is the linear average of vref(t) over a very long period of time (e.g.,1 sec). this average has to meet the min/max requirement in previous page. furthermore vref(t) may temporarily deviate from vref(dc) by no more than 1% vdd. the voltage levels for setup and hold time measurements vih(ac), vih(dc), vil(ac), and vil(dc) are dependent on vref. vref shall be understood as vref(dc). the clarifies that dc - variations of vref affect the absolute voltage a signal has to reach to ach ieve a valid high or low level and therefore the time to which setup and hold is measured. system timing and voltage budgets need to account for vref(dc) deviations from the optimum position within the data - eye of the input signals. this also clarifies tha t the dram setup/hold specification and de - rating values need to include time and voltage associated with vref ac - noise. timing and voltage effects due to ac - noise on vref up to the specified limit ( 1% of vdd) are included in dram timing and their associa ted de - ratings. illustration of v ref(dc) tolerance and v ref ac - noise limits vref ( dc ) vref ( dc ) max vref ( dc ) min vdd / 2 vref ac - noise voltage time vdd vss ddr3 (l) 2 gb sdram nt5c b( c ) 256 m8 f n / nt5cb(c) 128 m16 f p version 1. 6 95 nanya technology cooperation ? 0 4 / 201 4 all rights reserved. ddr3 differential ac and dc input levels for clock (ck - ?? ??? symbol parameter ddr3 - 800, 1066, 1333, & 1600 unit notes min max vihdiff differential input high + 0.200 note 3 v 1 vildiff differential input logic low note 3 - 0.200 v 1 vihdiff(ac) differential input high ac 2 x (vih(a c) - vref) note 3 v 2 vildiff(ac) differential input low ac note 3 2 x (vil(ac) - vref) v 2 note 1. used to define a differential signal slew - rate. note 2. for ck - ?? use vih/vil(ac) of add/cmd and vrefca; for dqs - ??? , dqsl, ???l , dqsu , ???u use vih/v il(ac) of dqs and vrefdq; if a reduced ac - high or ac - low level is used for a signal group,then the reduced level applies also here. note 3. these values are not defined; however, the single - ended signals ck, ?? , dqs, ??? , dqsl, ???l , dqsu, ???u need to be within the respective limits (vih(dc) max, vil(dc)min) for single - ended signals as well as the limitations for overshoot and undershoot. refer to overshoot and undershoot specifications ddr3l differential ac and dc input levels for clock (ck - ?? ??? symbol parameter ddr3l - 800, 1066, 1333, 1600 & 1866 unit notes min max vihdiff differential input high + 0. 18 0 note 3 v 1 vildiff differential input logic low note 3 - 0. 18 0 v 1 vihdiff(ac) differential input high ac 2 x (vih(a c) - vref) note 3 v 2 vildiff(ac) differential input low ac note 3 2 x (vil(ac) - vref) v 2 note 1 used to define a differential signal slew - rate. note 2 for ck - ?? use vih/vil(ac) of add/cmd and vrefca; for dqs - ??? , dqsl, ???l , dqsu , ???u use vih/vi l(ac) of dqs and vrefdq; if a reduced ac - high or ac - low level is used for a signal group, then the reduced level applies also here. note 3 these values are not defined, however the single - ended signals ck, ?? , dqs, ??? , dqsl, ???l , dqsu, ???u need to be wi thin the respective limits (vih(dc) max, vil(dc)min) for single - ended signals as well as the limitations for overshoot and undershoot. refer to overshoot and undershoot specifications. ddr3 (l) 2 gb sdram nt5c b( c ) 256 m8 f n / nt5cb(c) 128 m16 f p version 1. 6 96 nanya technology cooperation ? 0 4 / 201 4 all rights reserved. definition of differential ac - swing and time above ac - level time d i f f e r e n t i a l i n p u t v o l t a g e ( i . e . d q s C d q s , c k C c k ) tdvac tdvac half cycle vih . diff . ac . min vih . diff. dc min vil . diff . ac . max 0 vil . diff. dc max ddr3 (l) 2 gb sdram nt5c b( c ) 256 m8 f n / nt5cb(c) 128 m16 f p version 1. 6 97 nanya technology cooperation ? 0 4 / 201 4 all rights reserved. ddr3 allowed time before ringback (tdvac) for ck - ?? ??? slew rate [v/ns] ddr3 - 800 / 1066 / 1333 / 1600 ddr3 - 1866 / 2133 tdvac [ps] @ |vih/ldiff(ac)| = 350mv tdvac [ ps ] @ |vih/ldiff(ac)| = 300mv tdvac [ ps ] @ |vih/ldiff(ac)| = (dqs - ??? ) only tdvac [ ps ] @ |vih/ldiff(ac)| = 300mv tdvac [ ps ] @ |vih/ldiff(ac)| = (ck - ?? ) only min max min max min max min max min max > 4.0 75 - 175 - 214 - 134 - 139 - 4.0 57 - 170 - 214 - 134 - 139 - 3.0 50 - 167 - 191 - 112 - 118 - 2.0 38 - 119 - 146 - 67 - 77 - 1.8 34 - 102 - 131 - 52 - 63 - 1.6 29 - 81 - 113 - 33 - 45 - 1.4 22 - 54 - 88 - 9 - 23 - 1.2 note - 19 - 56 - note - note - 1.0 note - note - 11 - note - note - < 1.0 note - note - note - note - note - note 1. rising input differential signal shall become equal to or greater than vihdi ff(ac) level and falling input differential signal shall become equal to or less than vildiff(ac) level. ddr3 (l) 2 gb sdram nt5c b( c ) 256 m8 f n / nt5cb(c) 128 m16 f p version 1. 6 98 nanya technology cooperation ? 0 4 / 201 4 all rights reserved. ddr3l allowed time before ringback (tdvac) for ck - ?? ??? slew rate [v/ns] ddr3l - 800/1066/1333/1600 ddr3l - 1866 tdvac [ps] @|vih/ldiff(ac)| = 320 mv tdvac [ps] @|vih/ldiff(ac)| = 270 mv tdvac [ps] @|vih/ldiff(ac)| = 270 mv tdvac [ps] @|vih/ldiff(ac)| = 250 mv tdvac [ps] @|vih/ldiff(ac)| = 2 60 mv min max min max min max min max min max > 4.0 189 - 201 - 163 - 168 - 176 - 4.0 189 - 201 - 163 - 168 - 176 - 3.0 162 - 179 - 140 - 147 - 154 - 2.0 109 - 134 - 95 - 105 - 111 - 1.8 91 - 119 - 80 - 91 - 97 - 1.6 69 - 100 - 62 - 74 - 78 - 1.4 40 - 76 - 37 - 52 - 56 - 1.2 note - 44 - 5 - 22 - 24 - 1.0 note - note - note - note - note - < 1.0 note - note - note - note - note - note 1. rising input differential signal shall become equal to or greater than vihdiff(ac) level and falling input di fferential signal shall become equal to or less than vildiff(ac) level. ddr3 (l) 2 gb sdram nt5c b( c ) 256 m8 f n / nt5cb(c) 128 m16 f p version 1. 6 99 nanya technology cooperation ? 0 4 / 201 4 all rights reserved. single - ended requirements for differential signals each individual component of a differential signal (ck, dqs, dqsl, dqsu, ?? , ??? , ? ???l , or ???u ) has also to comply with ce rtain requirements for single - ended signals. ck and ?? have to approximately reach vsehmin / vselmax (approximately equal to the ac - levels (vih (ac) / vil (ac)) for add/cmd signals) in every half - cycle. dqs, dqsl, dqsu, ??? , ???l have to reach vsehmin / v selmax (approxi - mately the ac - levels (vih (ac) / vil (ac)) for dq signals) in every half - cycle proceeding and following a valid transition. note that the applicable ac - levels for add/cmd and dqs might be differ ent per speed - bin etc. e.g., if vih150 (ac)/ vil150(ac) is used for add/cmd signals, then these ac - levels apply also for the singleended signals ck and ?? ?? ddr3 (l) 2 gb sdram nt5c b( c ) 256 m8 f n / nt5cb(c) 128 m16 f p version 1. 6 100 nanya technology cooperation ? 0 4 / 201 4 all rights reserved. single - ended levels for ck, dqs, dqsl, dqsu, ?? ??? ???l ???u symbol parameter ddr3 (l) - 800, 1066, 1333, & 1600 unit notes min . max . vseh single - ended high - level for strobes (vddq/2) + 0.175 note3 v 1, 2 single - ended high - level for ck, ? ? (vddq/2) + 0.175 note3 v 1, 2 vsel single - ended low - level for strobes note3 (vddq/2) - 0.175 v 1, 2 single - ended low - level for ck, ?? note3 (vddq/2) - 0.175 v 1, 2 note: 1. for ck, ?? use vih/vil(ac) of add/cmd; for strobes (dqs, dqsl, dqsu, ck, ??? , ? ??l , or ???u ) use vih/vil(ac) of dqs. 2. vih(ac)/vil(ac) for dqs is based on vrefdq; vih(ac)/vil(ac) for add/cmd is based on vrefca; if a reduced ac - high or ac - low level is used for a signal group, then the reduced level applies also there. 3. these values are n ot defined, however the single - ended signals ck, ?? , dqs, ??? , dqsl, ???l , dqsu, ???u need to be within the respective limits (vih(dc)max, vil(dc)min) for single - ended signals as well as limitations for overshoot and undershoot. ddr3 (l) 2 gb sdram nt5c b( c ) 256 m8 f n / nt5cb(c) 128 m16 f p version 1. 6 101 nanya technology cooperation ? 0 4 / 201 4 all rights reserved. differential input cros s point voltage to guarantee tight setup and hold times as well as output skew parameters with respect to clock and strobe, each cross point voltage of differential input signals (ck, ?? and dqs, ??? ) must meet the requirements in the following table. the differential input cross point voltage vix is measured from the actual cross point of true and complete signal to the midleve l between of vdd and vss. vix definition cross point voltage for differential input signals (ck, dqs ) symbol parameter ddr3 ddr3l unit notes 800/1066/1333/1600/ 1866/2133 800 / 1066 / 1333 / 1600 / 1866 min max min max vix(ck) differential input cross point voltage relative to vdd/2 for ck, ?? - 150 + 150 - 150 + 150 mv 1 - 175 - 175 mv 2 vix(dqs) differential input cross point voltage relative to vdd/2 for dqs, ??? - 150 + 150 - 150 + 150 mv 1 note 1 the relation between vix min/max and vsel/vseh should satisfy following : (vdd/2) + v ix (min) - vsel >= 25 mv ; vseh - ((vdd/2) + v ix (max)) >= 25 mv ; note 2 extended range for vix is only allowed for clock and if single - ended clock input signals ck and ?? are monotonic with a single - ended swing vsel / vseh of at least vdd/2 +/ - 250 mv, a nd when the differential slew rate of ck - ?? is larger than 3 v/ns. v d d v s s v d d / 2 ? ? , ? ? ? c k , d q s v i x v i x v i x v s e h v s e l ddr3 (l) 2 gb sdram nt5c b( c ) 256 m8 f n / nt5cb(c) 128 m16 f p version 1. 6 102 nanya technology cooperation ? 0 4 / 201 4 all rights reserved. slew rate definition for differential input signals input slew rate for differential signals (ck, ?? and dqs, ??? ) are defined and measured as shown below. differential input slew rat e definition description measured defined by from to differential input slew rate for rising edge (ck - ??? & dqs - ??? ) vildiffmax vihdiffmin [vihdiffmin - vildiffmax] / deltatrdiff differential input slew rate for falling edge (ck - ?? & dqs - ??? ) vihdiffm in vildiffmax [vihdiffmin - vildiffmax] / deltatfdiff the differential signal (i.e., ck - ??? & dqs - ??? ) must be linear between these thresholds. ddr3 (l) 2 gb sdram nt5c b( c ) 256 m8 f n / nt5cb(c) 128 m16 f p version 1. 6 103 nanya technology cooperation ? 0 4 / 201 4 all rights reserved. input nominal slew rate definition for single ended signals a c and dc output measurement levels single ended ac and dc output levels symbol parameter ddr3 ( l ) unit notes voh(dc) dc output high measurement level (for iv curve linearity) 0.8xvddq v vom(dc) dc output mid measurement level (for iv curve linearity) 0 .5xvddq v vol(dc) dc output low measurement level (fro iv curve linearity) 0.2xvddq v voh(ac) ac output high measurement level (for output sr) vtt+0.1xvddq v 1 vol(ac) ac output low measurement level (for output sr) vtt - 0.1xvddq v 1 note: 1. the swing of 0.1 x vddq is based on approximately 50% of the static single ended output high or low swing with a driver impedance of 40 ? and an effective test load of 25 ? to vtt = vddq/2. differential ac and dc output levels symbol parameter ddr3 ( l ) unit notes vohdiff(ac) ac differential output high measurement level (for output sr) +0.2 x vddq v 1 voldiff(ac) ac differential output low measurement level (for output sr) - 0.2 x vddq v 1 note: 1. the swing of 0.2 x vddq is based on approximately 50% of the sta tic differential output high or low swing with a driver impedance of 40 ? and an effective test load of 25 ? to vtt=vddq/2 at each of the differential outputs. d e l t a t f d i f f d e l t a t r d i f f v i h d i f f m i n v i l d i f f m a x 0 ddr3 (l) 2 gb sdram nt5c b( c ) 256 m8 f n / nt5cb(c) 128 m16 f p version 1. 6 104 nanya technology cooperation ? 0 4 / 201 4 all rights reserved. single ended output slew rate description measured defined by from to single ended output slew rate for rising edge vol(ac) voh(ac) [voh(ac) - vol(ac)] / deltatr se single ended output slew rate for falling edge voh(ac) vol(ac) [voh(ac) - vol(ac)] / deltatfse note: output slew rate is verified by design and characterization, and may not be subject to production test. single ended output slew rate definition delta tfse delta tfse v oh ( ac ) v ol ( ac ) v tt s i n g l e e n d e d o u t p u t v o l t a g e ( i . e . d q ) ddr3 (l) 2 gb sdram nt5c b( c ) 256 m8 f n / nt5cb(c) 128 m16 f p version 1. 6 105 nanya technology cooperation ? 0 4 / 201 4 all rights reserved. output slew rate (single - ended) parameter symbol - 800 1066 1333 1600 1866 2133 unit min max min max min max min max min max min max single - ended output slew rate srqse ddr3 2.5 5 2.5 5 2.5 5 2.5 5 2.5 5 2.5 5 v/ns ddr 3l 1.75 5 1.75 5 1.75 5 1.75 5 1.75 5 1.75 5 v/ns description: sr: slew rate q: query output (like in dq, which stands for data - in, query - output) se: single - ended signals for ron = rzq/7 setting note 1): in two cases, a maximum slew rate of 6v/ns applies for a single dq signal within a byte lane. case 1 is defined for a single dq signal within a byte lane which is switching into a certain direction (either from high to low or low to high) while all remaining dq signals in the same byte lane are static (i. e. they stay at either high or low). case 2 is defined for a single dq signal within a byte lane which is switching into a certain direction (either from high to low or low to high) while all remaining dq signals in the same byte lane are switching into th e opposite direction (i.e. from low to high or high to low respectively). for the remaining dq signal switching into the opposite direction, the regular maximum limit of 5 v/ns applies . ddr3 (l) 2 gb sdram nt5c b( c ) 256 m8 f n / nt5cb(c) 128 m16 f p version 1. 6 106 nanya technology cooperation ? 0 4 / 201 4 all rights reserved. differential output slew rate description measured defined by f rom to differential output slew rate for rising edge voldiff(ac) vohdiff(ac) [vohdiff(ac) - voldiff(ac)] / deltatrdiff differential output slew rate for falling edge vohdiff(ac) voldiff(ac) [vohdiff(ac) - voldiff(ac)] / deltatfdiff note: output slew rat e is verified by design and characterization, and may not be subject to production test. differential output slew rate definition output slew rate ( differential ) parameter symbol - 800 1066 1333 1600 1866 2133 unit min max min max min max min max min max min max differential output slew rate srqdiff ddr3 5 10 5 10 5 10 5 10 5 10 5 10 v/ns ddr3l 3.5 12 3.5 12 3.5 12 3.5 12 3.5 12 3.5 12 v/ns description: sr: slew rate q: query output (like in dq, which stands for d ata - in, query - output) diff: differential signals for ron = rzq/7 setting delta tfse delta tfse v oh diff ( ac ) v ol diff ( ac ) 0 d i f f e r e n t i a l o u t p u t v o l t a g e ( i . e . d q s - d q s ) ddr3 (l) 2 gb sdram nt5c b( c ) 256 m8 f n / nt5cb(c) 128 m16 f p version 1. 6 107 nanya technology cooperation ? 0 4 / 201 4 all rights reserved. reference load for ac timing and output slew rate the following figure represents the effective reference load of 25 ohms used in defining the relevant ac timing parameters of the de vice as well as output slew rate measurements. it is not intended as a precise representation of any particular system environment or a depiction of the actual load presented by a production tester. system designers should use ibis or other simulation tool s to correlate the timing reference load to a system environment. manufacturers correlate to their production test conditions, generally one or more coaxial transmission lines terminated at the tester electronics. v t t = v d d q / 2 2 5 o h m c k , ? ? v d d q d u t d q d q s ? ? ? t i m i n g r e f e r e n c e p o i n t s ddr3 (l) 2 gb sdram nt5c b( c ) 256 m8 f n / nt5cb(c) 128 m16 f p version 1. 6 108 nanya technology cooperation ? 0 4 / 201 4 all rights reserved. overshoot and undershoot specifications ac overshoot/undershoot specification for address and control pins - 800 1066 1333 1600 1866 2133 unit maximum peak amplitude allowed for overshoot area 0.4 0.4 0.4 0.4 0.4 0.4 v maximum peak amplitude allowed for undershoot ar ea. 0.4 0.4 0.4 0.4 0.4 0.4 v maximum overshoot area above vdd 0.67 0.5 0.4 0.33 0.28 0.25 v - ns maximum undershoot area below vss 0.67 0.5 0.4 0.33 0.28 0.25 v - ns note 1. the sum of the applied voltage (vdd) and peak amplitude overshoot voltage is not t o exceed absolute maximum dc ratings note 2. the sum of applied voltage (vdd) and the peak amplitude undershoot voltage is not to exceed absolute maximum dc ratin gs v d d v s s o v e r s h o o t a r e a u n d e r s h o o t a r e a m a x i m u m a m p l i t u d e m a x i m u m a m p l i t u d e t i m e ( n s ) v o l t s ( v ) ddr3 (l) 2 gb sdram nt5c b( c ) 256 m8 f n / nt5cb(c) 128 m16 f p version 1. 6 109 nanya technology cooperation ? 0 4 / 201 4 all rights reserved. overshoot and undershoot specifications ac overshoot/undershoot specification for cloc k, data, strobe and mask 800 1066 1333 1600 1866 2133 unit maximum peak amplitude allowed for overshoot area 0.4 0.4 0.4 0.4 0.4 0.4 v maximum peak amplitude allowed for undershoot area. 0.4 0.4 0.4 0.4 0.4 0.4 v maximum overshoot area above vdd 0.25 0 .19 0.1 5 0.13 0.1 1 0.10 v - ns maximum undershoot area below vss 0.25 0.19 0.1 5 0.13 0.1 1 0.10 v - ns note 1. the sum of the applied voltage (vdd) and peak amplitude overshoot voltage is not to exceed absolute maximum dc rating s note 2. the sum of applied vo ltage (vdd) and the peak amplitude undershoot voltage is not to exceed absolute maximum dc ratings v d d q v s s q o v e r s h o o t a r e a u n d e r s h o o t a r e a m a x i m u m a m p l i t u d e m a x i m u m a m p l i t u d e t i m e ( n s ) v o l t s ( v ) ddr3 (l) 2 gb sdram nt5c b( c ) 256 m8 f n / nt5cb(c) 128 m16 f p version 1. 6 110 nanya technology cooperation ? 0 4 / 201 4 all rights reserved. 34 ohm output driver dc electrical characteristics a functional representation of the output buffer is shown as below. output driver impedance ron is def ined by the value of the external reference resistor rzq as follows: ron 34 = r zq / 7 (nominal 34.4ohms +/ - 10% with nominal r zq =240ohms) the individual pull - up and pull - down resistors (ron pu and ron pd ) are defined as follows: under the conditio n that ron pd is turned off (1) under the condition that ron pu is turned off (2) output driver: definition of voltages and currents | i out | vddq C v out ron pu = | i out | v out ron p d = ddr3 (l) 2 gb sdram nt5c b( c ) 256 m8 f n / nt5cb(c) 128 m16 f p version 1. 6 111 nanya technology cooperation ? 0 4 / 201 4 all rights reserved. output driver dc electrical characteristics, assuming r zq = 240ohms; entire operating temperature range ; after proper zq calibration ron nom resistor vout min . nom . max . unit notes ddr3l 34 ohms ron34 pd voldc = 0.2 x vddq 0.6 1 .0 1.1 5 r zq / 7 1,2,3 vomdc = 0.5 x vddq 0.9 1 .0 1.1 5 r zq / 7 1,2,3 vohdc = 0.8 x vddq 0.9 1 .0 1.4 5 r zq / 7 1,2,3 ron34 pu v oldc = 0.2 x vddq 0.9 1 .0 1.4 5 r zq / 7 1,2,3 vomdc = 0.5 x vddq 0.9 1 .0 1.1 5 r zq / 7 1,2,3 vohdc = 0.8 x vddq 0.6 1 .0 1.1 5 r zq / 7 1,2,3 4 0 ohms ron40 pd v oldc = 0.2 v ddq 0.6 1.0 1.15 r zq / 6 1,2,3 vomdc = 0.5 vddq 0.9 1.0 1.15 r zq / 6 1,2,3 vohdc = 0.8 vddq 0.9 1.0 1.45 r zq / 6 1,2,3 ron40 pu voldc = 0.2 vddq 0.9 1.0 1.45 r zq / 6 1,2,3 vomdc = 0.5 vddq 0.9 1.0 1.15 r zq / 6 1,2,3 vohdc = 0.8 vddq 0.6 1.0 1.15 r zq / 6 1,2,3 mismatch between pull - up and pull - down, mm pupd vomdc = 0.5 x vddq - 10 +10 % 1,2,4 ddr3 34 ohms ron34 pd voldc = 0.2 x vddq 0.6 1 .0 1.1 r zq / 7 1,2,3 vomdc = 0.5 x vddq 0.9 1 .0 1.1 r zq / 7 1,2,3 vohdc = 0.8 x vddq 0.9 1 .0 1.4 r zq / 7 1,2,3 ron34 pu voldc = 0.2 x vddq 0.9 1 .0 1.4 r zq / 7 1,2,3 vomd c = 0.5 x vddq 0.9 1 .0 1.1 r zq / 7 1,2,3 vohdc = 0.8 x vddq 0.6 1 .0 1.1 r zq / 7 1,2,3 4 0 ohms ron40 p d v oldc = 0.2 v ddq 0.6 1.0 1.1 r zq / 6 1,2,3 v omdc = 0.5 v ddq 0.9 1.0 1.1 r zq / 6 1,2,3 v ohdc = 0.8 v ddq 0.9 1.0 1.4 r zq / 6 1,2,3 ron40 p u v oldc = 0.2 v ddq 0.9 1.0 1.4 r zq / 6 1,2,3 v omdc = 0.5 v ddq 0.9 1.0 1.1 r zq / 6 1,2,3 v ohdc = 0.8 v ddq 0.6 1.0 1.1 r zq / 6 1,2,3 mismatch between pull - up and pull - down, mm pupd vomdc = 0.5 x vddq - 10 + 10 % 1,2,4 ddr3 (l) 2 gb sdram nt5c b( c ) 256 m8 f n / nt5cb(c) 128 m16 f p version 1. 6 112 nanya technology cooperation ? 0 4 / 201 4 all rights reserved. note 1. the tolerance limits are specified after calibration with stable voltage and temperature. for the behavior of the tolerance limits if temperature or voltage changes after calibration, see following section on voltage and temperature sensitivity. note 2. the tolerance limits ar e specified under the condition that vddq = vdd and that vssq = vss. note 3. pull - down and pull - up output driver impedances are recommended to be calibrated at 0.5 x vddq. other calibration schemes may be used to achieve the linearity spec shown above, e. g. calibration at 0.2 x vddq and 0.8 x vddq. note 4. measurement definition for mismatch between pull - up and pull - down, mmpupd: measure ronpu and ronpd, both at 0.5 * vddq: ron nom ron pu C ron pd mm pu pd = x 100 ddr3 (l) 2 gb sdram nt5c b( c ) 256 m8 f n / nt5cb(c) 128 m16 f p version 1. 6 113 nanya technology cooperation ? 0 4 / 201 4 all rights reserved. output driver temperature and voltage sensitivity if temperature and/or volt age after calibration, the tolerance limits widen according to the following table. delta t = t - t(@calibration); delta v = vddq - vddq(@calibration); vdd = vddq note: dr on dt and dr on dv are not subject to production test but are verified by design and cha racterization. output driver sensitivity definition items m in . m ax . unit ronpu@vohdc 0.6 - dr on dth*ldelta tl - dr on dvh*ldelta vl 1.1 + dr on dth*ldelta tl - dr on dvh*ldelta vl r zq /7 ron@vomdc 0.9 - dr on dtm*ldelta tl - dr on dvm*ldelta vl 1.1 + dr on dtm*ldelta tl - dr on dvm*ldelta vl r zq /7 ronpd@voldc 0.6 - dr on dtl*ldelta tl - dr on dvl*ldelta vl 1.1 + dr on dtl*ldelta tl - dr on dvl*ldelta vl r zq /7 output driver voltage and temperature sensitivity speed bin ddr3(l) - 800/1066/1333 ddr3(l) - 1600 unit items m in . m ax . m in . m ax . drondtm 0 1.5 0 1.5 %/ ? c drondvm 0 0.15 0 0.13 %/mv drondtl 0 1.5 0 1.5 %/ ? c drondvl 0 0.15 0 0.13 %/mv drondth 0 1.5 0 1.5 %/ ? c drondvh 0 0.15 0 0.13 %/mv note: these parameters may not be subject to production test. they are verified by design and characterization. ddr3 (l) 2 gb sdram nt5c b( c ) 256 m8 f n / nt5cb(c) 128 m16 f p version 1. 6 114 nanya technology cooperation ? 0 4 / 201 4 all rights reserved. on - die termination (odt) levels and i - v characteristics on - die termination effective resistance rtt is defined by bits a9, a6, and a2 of the mr1 register. odt is applied to the dq, dm, dqs/ ??? , and tdqs/ t??? (x8 devices only) pins. a functional representation of the on - die termination is shown in the following figure. the individual pull - up and pull - down resistors (rtt pu and rtt pd ) are defined as follows: under the condition that r tt pd is turned off ( 3 ) under the condition that r tt pu is turned off ( 4 ) on - die termination: definition of voltages and currents | i out | vddq C v out r tt pu = | i out | v out r tt p d = ddr3 (l) 2 gb sdram nt5c b( c ) 256 m8 f n / nt5cb(c) 128 m16 f p version 1. 6 115 nanya technology cooperation ? 0 4 / 201 4 all rights reserved. odt dc electrical characteristics the following table provides an overview of the odt dc electrical cha racteristics. the values for rtt 60pd120 , rtt 60pu120 , rtt 120pd240 , rtt 120pu240 , rtt 40pd80 , rtt 40pu80 , rtt 30pd60 , rtt 30pu60 , rtt 20pd40 , rtt 20pu40 are not specification requirements, but can be used as design guide lines: odt dc electrical characteristics, a ssuming r zq = 240ohms +/ - 1% entire operating temperature range; after proper zq calibration (ddr3l) mr1 a9,a6,a2 rtt resistor vout min . nom . max . unit notes ddr3l 0,1,0 120? rtt 120pd240 voldc = 0.2 x vddq 0.6 1 1.1 5 r zq 1,2,3,4 0.5 x vddq 0.9 1 1.1 5 r zq 1,2,3,4 vohdc = 0.8 x vddq 0.9 1 1.4 5 r zq 1,2,3,4 rtt 120pu240 voldc = 0.2 x vddq 0.9 1 1.4 5 r zq 1,2,3,4 0.5 x vddq 0.9 1 1 . 1 5 r zq 1,2,3,4 vohdc = 0.8 x vddq 0.6 1 1.1 5 r zq 1,2,3,4 rtt 120 vil(ac) to vih(ac) 0.9 1 1.6 5 r zq /2 1,2,5 0, 0, 1 60? rtt 60pd120 voldc = 0.2 x vddq 0.6 1 1.1 5 r zq /2 1,2,3,4 0.5 x vddq 0.9 1 1.1 5 r zq /2 1,2,3,4 vohdc = 0.8 x vddq 0.9 1 1.4 5 r zq /2 1,2,3,4 rtt 60pu120 voldc = 0.2 x vddq 0.9 1 1.4 5 r zq /2 1,2,3,4 0.5 x vddq 0.9 1 1.1 5 r zq /2 1,2,3,4 vohdc = 0.8 x vddq 0.6 1 1.1 5 r zq /2 1,2,3,4 rtt 60 vil(ac) to vih(ac) 0.9 1 1.6 5 r zq /4 1,2,5 0, 1, 1 40? rtt 40pd80 voldc = 0.2 x vddq 0.6 1 1.1 5 r zq /3 1,2,3,4 0.5 x vddq 0.9 1 1.1 5 r zq /3 1,2,3,4 vohdc = 0.8 x vddq 0.9 1 1.4 5 r zq /3 1,2,3,4 rtt 40pu80 voldc = 0.2 x vddq 0.9 1 1.4 5 r zq /3 1,2,3,4 0.5 x vddq 0.9 1 1.1 5 r zq /3 1,2,3,4 vohdc = 0.8 x vddq 0.6 1 1.1 5 r zq /3 1,2,3,4 rtt 40 vil(ac) to vih(ac) 0.9 1 1.6 5 r zq /6 1,2,5 1, 0, 1 30? rtt 30pd60 voldc = 0.2 x vddq 0.6 1 1.1 5 r zq /4 1,2,3,4 0. 5 x vddq 0.9 1 1.1 5 r zq /4 1,2,3,4 vohdc = 0.8 x vddq 0.9 1 1.4 5 r zq /4 1,2,3,4 rtt 30pu60 voldc = 0.2 x vddq 0.9 1 1.4 5 r zq /4 1,2,3,4 0.5 x vddq 0.9 1 1.1 5 r zq /4 1,2,3,4 vohdc = 0.8 x vddq 0.6 1 1.1 5 r zq /4 1,2,3,4 rtt 30 vil(ac) to vih(ac) 0 .9 1 1.6 5 r zq /8 1,2,5 1, 0, 0 20? rtt 20pd40 voldc = 0.2 x vddq 0.6 1 1.1 5 r zq /6 1,2,3,4 0.5 x vddq 0.9 1 1.1 5 r zq /6 1,2,3,4 vohdc = 0.8 x vddq 0.9 1 1.4 5 r zq /6 1,2,3,4 rtt 20pu40 voldc = 0.2 x vddq 0.9 1 1.4 5 r zq /6 1,2,3,4 0.5 x vddq 0.9 1 1.1 5 r zq /6 1,2,3,4 vohdc = 0 .8 x vddq 0.6 1 1.1 5 r zq /6 1,2,3,4 rtt 20 vil(ac) to vih(ac) 0.9 1 1.6 5 r zq /12 1,2,5 deviation of v m w.r.t. v ddq/2, d v m - 5 +5 % 1,2,5,6 ddr3 (l) 2 gb sdram nt5c b( c ) 256 m8 f n / nt5cb(c) 128 m16 f p version 1. 6 116 nanya technology cooperation ? 0 4 / 201 4 all rights reserved. odt dc electrical characteristics, assuming r zq = 240ohms +/ - 1% entire operating temperature range; after proper zq calibration (ddr3) mr1 a9,a6,a2 rtt resistor vout min . nom . max . unit notes ddr3 0,1,0 120? rtt 120pd240 voldc = 0.2 x vddq 0.6 1 1.1 r zq 1,2,3,4 0.5 x vddq 0.9 1 1.1 r zq 1,2,3,4 vohdc = 0.8 x vddq 0.9 1 1.4 r zq 1,2,3,4 rtt 120pu240 voldc = 0.2 x vddq 0.9 1 1.4 r zq 1,2,3,4 0.5 x vddq 0.9 1 1,1 r zq 1,2,3,4 vohdc = 0.8 x vddq 0.6 1 1.1 r zq 1,2,3,4 rtt 120 vil(ac) to vih(ac) 0.9 1 1.6 r zq /2 1,2,5 0, 0, 1 60? rtt 60pd120 voldc = 0.2 x vddq 0.6 1 1.1 r zq /2 1,2,3,4 0.5 x vddq 0.9 1 1.1 r zq /2 1,2,3,4 vohdc = 0.8 x vddq 0.9 1 1.4 r zq /2 1,2,3,4 rtt 60pu120 voldc = 0.2 x v ddq 0.9 1 1.4 r zq /2 1,2,3,4 0.5 x vddq 0.9 1 1.1 r zq /2 1,2,3,4 vohdc = 0.8 x vddq 0.6 1 1.1 r zq /2 1,2,3,4 rtt 60 vil(ac) to vih(ac) 0.9 1 1.6 r zq /4 1,2,5 0, 1, 1 40? rtt 40pd80 voldc = 0.2 x vddq 0.6 1 1.1 r zq /3 1,2,3,4 0.5 x vddq 0.9 1 1.1 r zq /3 1,2,3,4 vohdc = 0.8 x vddq 0.9 1 1.4 r zq /3 1,2,3,4 rtt 40pu80 voldc = 0.2 x vddq 0.9 1 1.4 r zq /3 1,2,3,4 0.5 x vddq 0.9 1 1.1 r zq /3 1,2,3,4 vohdc = 0.8 x vddq 0.6 1 1.1 r zq /3 1,2,3,4 rtt 40 vil(ac) to vih(ac) 0.9 1 1.6 r zq /6 1,2,5 1, 0, 1 30? rtt 30pd60 voldc = 0.2 x vddq 0.6 1 1.1 r zq /4 1,2,3,4 0.5 x vddq 0.9 1 1.1 r zq /4 1,2,3,4 vohdc = 0.8 x vddq 0.9 1 1.4 r zq /4 1,2,3,4 rtt 30pu60 voldc = 0.2 x vddq 0.9 1 1.4 r zq /4 1,2,3,4 0.5 x vddq 0.9 1 1.1 r zq /4 1,2,3,4 vohdc = 0.8 x vddq 0.6 1 1.1 r zq /4 1,2,3,4 rtt 30 vil(ac) to vih(ac) 0.9 1 1.6 r zq /8 1,2,5 1, 0, 0 20? rtt 20pd40 voldc = 0.2 x vddq 0.6 1 1.1 r zq /6 1,2,3,4 0.5 x vddq 0.9 1 1.1 r zq /6 1,2,3,4 vohdc = 0.8 x vddq 0.9 1 1.4 r zq /6 1,2,3,4 rtt 20pu40 voldc = 0.2 x vddq 0.9 1 1.4 r zq /6 1,2,3,4 0.5 x vddq 0.9 1 1.1 r zq /6 1,2,3,4 vohdc = 0.8 x vddq 0.6 1 1.1 r zq /6 1,2,3,4 rtt 20 vil(ac) to vih(ac) 0.9 1 1.6 r zq /12 1,2,5 deviation of v m w.r.t. v ddq/2, d v m - 5 +5 % 1,2,5,6 ddr3 (l) 2 gb sdram nt5c b( c ) 256 m8 f n / nt5cb(c) 128 m16 f p version 1. 6 117 nanya technology cooperation ? 0 4 / 201 4 all rights reserved. note 1. the tolerance limits are s pecified after calibration with stable voltage and temperature. for the behavior of the tolerance limits if temperature or voltage changes after calibration, see following section on voltage and temperature sensitivity. note 2. the tolerance limits are spe cified under the condition that v ddq = v dd and that v ssq = v ss. note 3. pull - down and pull - up odt resistors are recommended to be calibrated at 0.5 x v ddq. other calibration schemes may be used to achieve the linearity spec shown above, e.g. calibration at 0.2 x v ddq and 0.8 x v ddq. note 4. not a specification requirement, but a design guide line. note 5. measurement definition for rtt : apply v ih(ac) to pin under test and measure current i ( v ih(ac)), then apply v il(ac) to pin under test and measure current i ( v il(ac)) respectively. note 6. measurement definition for v m and d v m: measure voltage ( v m) at test pin (midpoint) with no load: r tt = i( v ih(ac)) C i( v il(ac)) v ih(ac) C v il(ac) vm = ( C 1) x 100 vddq 2 x vm ddr3 (l) 2 gb sdram nt5c b( c ) 256 m8 f n / nt5cb(c) 128 m16 f p version 1. 6 118 nanya technology cooperation ? 0 4 / 201 4 all rights reserved. odt temperature and voltage sensitivity if temperature and/or voltage after calibration, the tolerance limits widen according to the following table. delta t = t - t(@calibration); delta v = vddq - vddq(@calibration); vdd = vddq odt sensitivity definition min . max . unit rtt 0.9 C dr tt dt * l tl C dr tt dv * l vl 1.6 + dr tt dt * l tl + dr tt dv * l vl rzq/2,4,6,8,12 odt voltage and temperature sensitivity min . max . unit drttdt 0 1.5 %/ ? c drttdv 0 0.15 %/mv note: these parameters may not be subject to pr oduction test. they are verified by design and characterization. test load for odt timings different than for timing measurements, the reference load for odt timings is defined in the following figure. odt timing reference l oad v t t = 2 5 o h m c k , v d d q d u t t i m i n g r e f e r e n c e p o i n t s v s s q r t t = d q , d m d q s , ? ? ? t d q s , t ? ? ? v s s q ? ? ddr3 (l) 2 gb sdram nt5c b( c ) 256 m8 f n / nt5cb(c) 128 m16 f p version 1. 6 119 nanya technology cooperation ? 0 4 / 201 4 all rights reserved. odt timing definitions definitions for t aon , t aonpd , t aof , t aofpd , and t adc are provided in the following table and subsequent figures. symbol begin point definition end point definition taon rising edge of ck - ck defined by the end point of odtlon extrapolated point at vssq taonpd rising edge of ck - ck with odt being first registered high extrapolated point at vssq taof rising edge of ck - ck defined by the end point of odtloff end point: extrapolated point at vrtt_nom taofpd rising edge of ck - ck with odt being first registered low end point: extrapolated point at vrtt_nom tadc rising edge of ck - ck defined by the end point of odtlcnw, odtlcwn4, or odtlcwn8 end point: extrapolated point at vrtt_wr and vrtt_nom respectively reference settin gs for odt timing measurements parameter rtt_nom rtt_wr ddr3 ddr3l vsw1[v] vsw2[v] vsw1[v] vsw2[v] taon rzq/4 na 0.05 0.10 0.05 0.10 rzq/12 na 0.10 0.20 0.10 0.20 taonpd rzq/4 na 0.05 0.10 0.05 0.10 rzq/12 na 0.10 0.20 0.10 0.20 taof rzq/4 na 0. 05 0.10 0.05 0.10 rzq/12 na 0.10 0.20 0.10 0.20 taofpd rzq/4 na 0.05 0.10 0.05 0.10 rzq/12 na 0.10 0.20 0.10 0.20 tadc rzq/12 rzq/2 0.20 0.30 0.20 0.2 5 definition of t aon taon tsw 2 tsw 1 vsw 1 vsw 2 vssq vtt dq , dm dqs , dqs # tdqs , tdqs # end point : extrapolated point at vssq ck ck # begin point : rising edge of ck C ck # defined by the end point of odtlon ddr3 (l) 2 gb sdram nt5c b( c ) 256 m8 f n / nt5cb(c) 128 m16 f p version 1. 6 120 nanya technology cooperation ? 0 4 / 201 4 all rights reserved. definition of t aonpd definition of t aof taonpd tsw 2 tsw 1 vsw 1 vsw 2 vssq vtt dq , dm dqs , dqs # tdqs , tdqs # end point : extrapolated point at vssq ck ck # begin point : rising edge of ck C ck # with odt being first register high taof tsw 2 tsw 1 vsw 1 vsw 2 vssq vtt dq , dm dqs , dqs # tdqs , tdqs # end point : extrapolated point at vrtt _ nom ck ck # begin point : rising edge of ck C ck # defined by the end point of odtloff vrtt _ nom ddr3 (l) 2 gb sdram nt5c b( c ) 256 m8 f n / nt5cb(c) 128 m16 f p version 1. 6 121 nanya technology cooperation ? 0 4 / 201 4 all rights reserved. definition of t aofpd definition of t adc taofpd tsw 2 tsw 1 vsw 1 vsw 2 vssq vtt dq , dm dqs , dqs # tdqs , tdqs # end point : extrapolated point at vrtt _ nom ck ck # begin point : rising edge of ck C ck # with odt being first registered low vrtt _ nom tadc tsw 21 tsw 11 vsw 1 vsw 2 dq , dm dqs , dqs # tdqs , tdqs # end point : extrapolated point at vrtt _ nom ck ck # begin point : rising edge of ck C ck # defined by the end of odtlcnw vrtt _ nom tadc tsw 22 tsw 12 vssq vtt end point : extrapolated point at vrtt _ wr ck ck # begin point : rising edge of ck C ck # defined by the end of odtlcwn 4 or odtlcwn 8 vrtt _ wr vrtt _ nom ddr3 (l) 2 gb sdram nt5c b( c ) 256 m8 f n / nt5cb(c) 128 m16 f p version 1. 6 122 nanya technology cooperation ? 0 4 / 201 4 all rights reserved. input/output capacitance parameter symbol 800 1066 1333 1600 1866 2133 unit notes min max min max min max min max min max mi n max input/output capacitance (dq, dm, dqs, ??? , tdqs, t??? ) cio (ddr3) 1.4 3.0 1.4 2.7 1.4 2.5 1.4 2.3 1.4 2.2 1.4 2.1 pf 1,2,3 cio (ddr3l) 1.4 2.5 1.4 2.5 1.4 2.3 1.4 2.2 1.4 2.1 - - pf 1,2,3 input capacitance, ck and ?? cck 0.8 1.6 0.8 1.6 0.8 1.4 0.8 1.4 0.8 1.3 0.8 1.3 pf 2,3 input capacitan ce delta, ck and ?? cdck 0 0.15 0 0.15 0 0.15 0 0.15 0 0.15 0 0.15 pf 2,3,4 input/output capacitance delta dqs and ??? cddqs 0 0.15 0 0.15 0 0.15 0 0.15 0 0.15 0 0.15 pf 2,3,5 input capacitance, (ctrl, add,cmd input - only pins) ci (ddr3) 0.75 1.4 0.75 1. 35 0.75 1.3 0.75 1.3 0.75 1.2 0.75 1.2 pf 2,3,6 ci (ddr3l) 0.75 1.3 0.75 1.3 0.75 1.3 0.75 1.2 0.75 1.2 - - pf 2,3,6 input capacitance delta, (all ctrl input - only pins cdi_ctrl - 0.5 0.3 - 0.5 0.3 - 0.4 0.2 - 0.4 0.2 - 0.4 0.2 - 0.4 0.2 pf 2,3,7,8 input cap acitance delta, (all add/cmd input - only pins) cdi_add_ cmd - 0.5 0.5 - 0.5 0.5 - 0.4 0.4 - 0.4 0.4 - 0.4 0.4 - 0.4 0.4 pf 2,3,9, 10 input/output capacitance delta , dq, dm, dqs, ??? , tdqs, t??? cdio - 0.5 0.3 - 0.5 0.3 - 0.5 0.3 - 0.5 0.3 - 0.5 0.3 - 0.5 0.3 pf 2,3,11 input/output capacitance of zq pin czq - 3 - 3 - 3 - 3 - 3 - 3 pf 2,3,12 note 1. although the dm, tdqs and t??? pins have different functions, the loading matches dq and dqs note 2. this parameter is not subject to production test. it is verified by design and characterization. the capacitance is measured according to jep147(procedure for measuring input capacitance using a vector network analyzer(vna)) with vdd, vddq, vss, vssq applied and all other pins floating (except the pin under test, cke, re?et and odt as necessary). vdd=vddq=1.5v, vbias=vdd/2 and ondie termination off. note 3. this parameter applies to monolithic devices only; stacked/dual - die devices are not covered here note 4. absolute value of cck - ??? note 5. absolute value of cio(dqs) - cio( ??? ) note 6. ci applies to odt, ?? , cke, a0 - a1 4 , ba0 - ba2, ra? , ?a? , we . note 7. cdi_ctrl applies to odt, ?? and cke note 8. cdi_ctrl=ci(ctrl) - 0.5*(ci(clk)+ci( ?l? )) note 9. cdi_add_cmd applies to a0 - a1 4 , ba0 - ba2, ra? , ?a? and we note 10. cdi_add_cmd=ci (add_cmd) - 0.5*(ci(clk)+ci( ?l? )) note 11. cdio=cio(dq,dm) - 0.5*(cio(dqs)+cio( ??? )) note 12. maximum external load capacitance on zq pin: 5 pf. ddr3 (l) 2 gb sdram nt5c b( c ) 256 m8 f n / nt5cb(c) 128 m16 f p version 1. 6 123 nanya technology cooperation ? 0 4 / 201 4 all rights reserved. ddr3l idd currents symbol parameter/condition ddr3l - 1600 (11 - 11 - 11) ddr3l - 1866 (13 - 13 - 13) unit x8 x16 x8 x16 idd0 operating current 0 one bank activate - > precharge 62 67 67 72 ma idd1 operating current 1 one bank activate - > read - > precharge 71 76 76 81 ma idd2p0 precharge power - down current slow exit - mr0 bit a12 = 0 11 11 ma idd2p1 precharge power - down current fast exit - mr0 bit a12 = 1 20 23 ma idd2q precharge quiet standby current 32 37 ma idd2n precharge standby current 32 37 ma idd2n t precharge standby odt current 37 40 42 45 ma idd3p active power - down current always fast exit 32 37 ma idd3n a ctive standby current 42 45 47 50 ma idd4r operating current burst read 140 150 150 160 ma idd4w operating current burst write 145 155 155 165 ma idd5b burst refresh current 135 140 ma idd6 tc 1 (rs - dib) self - refresh current : room temperature r ange 3 3 ma idd6 2 self - refresh current normal 11 11 ma idd6et 3 self - refresh current : extended 14 14 ma idd7 all bank interleave read current 210 220 220 230 ma idd8 reset low current 13 13 ma note 1 idd6 tc (rs - dib ):t c room temperature; srt is disabled, asr is enabled. value is maximum. note 2 idd6: srt is normal , asr is disabled. value is maximum. - commercial grade = 0 ~ 8 5 - industrial grade ( - i ) = - 40 ~ 8 5 - automotive grade 2 ( - h ) = - 40 ~ 8 5 - automotive grade 3 ( - a ) = - 40 ~ 8 5 note 3 idd6et: srt is extended , asr is disabled. value is maximum. - commercial grade = 0 ~ 95 - industrial grade ( - i ) = - 40 ~ 9 5 - automotive grade 2 ( - h ) = - 40 ~ 10 5 - automotive grade 3 ( - a ) = - 40 ~ 9 5 ddr3 (l) 2 gb sdram nt5c b( c ) 256 m8 f n / nt5cb(c) 128 m16 f p version 1. 6 124 nanya technology cooperation ? 0 4 / 201 4 all rights reserved. ddr3 idd currents symbol parameter/condition ddr3 - 1600 (11 - 11 - 11) ddr3 - 1866 (12 - 12 - 12) ddr3 - 1866 (13 - 13 - 13) ddr3 - 2133 (14 - 14 - 14) unit x8 x16 x8 x16 x8 x16 x8 x16 idd0 operating current 0 one bank activate - > precharge 65 70 70 75 70 75 75 80 ma idd1 operating current 1 one b ank activate - > read - > precharge 75 80 80 85 80 85 85 90 ma idd2p0 precharge power - down current slow exit - mr0 bit a12 = 0 12 12 12 12 ma idd2p1 precharge power - down current fast exit - mr0 bit a12 = 1 22 25 25 28 ma idd2q precharge quiet standby curren t 35 40 40 45 ma idd2n precharge standby current 35 40 40 45 ma idd2n t precharge standby odt current 40 43 45 48 45 48 50 53 ma idd3p active power - down current always fast exit 35 40 40 45 ma idd3n active standby current 45 48 50 53 50 53 55 58 ma idd 4r operating current burst read 145 155 155 165 155 165 165 175 ma idd4w operating current burst write 150 160 160 170 160 170 170 180 ma idd5b burst refresh current 145 150 150 155 ma idd6 1 self - refresh current normal 12 ma idd6et 2 self - refresh current extended 15 ma idd7 all bank interleave read current 230 240 240 250 240 250 250 260 ma idd8 reset low current 14 ma note 1 idd6: srt is normal , asr is disabled. value is maximum. - commercial grade = 0 ~ 8 5 - industrial grade ( - i ) = - 40 ~ 8 5 - automotive grade 2 ( - h ) = - 40 ~ 8 5 - automotive grade 3 ( - a ) = - 40 ~ 8 5 note 2 idd6et: srt is ex tended , asr is disabled. value is maximum. - commercial grade = 0 ~ 95 - industrial grade ( - i ) = - 40 ~ 9 5 - automotive grade 2 ( - h ) = - 40 ~ 10 5 - automotive grade 3 ( - a ) = - 40 ~ 9 5 ddr3 (l) 2 gb sdram nt5c b( c ) 256 m8 f n / nt5cb(c) 128 m16 f p version 1. 6 125 nanya technology cooperation ? 0 4 / 201 4 all rights reserved. idd measurement conditions symbol parameter/condition idd0 operating one bank active - precharge current cke: high; external clock: on; tck, nrc, nras, cl: see the table of timings used for idd and iddq ; bl: 8 (1) ; al: 0; ?? :high between act and pre; command, address, bank address inputs: partially toggling; data io: mid - level; dm :stable at 0; bank activity: cycling with one bank active at a time: 0,0,1,1,2,2,...; output buffer and rtt: enabled in mode registers (2) ; o dt signal: stable at 0; idd1 operating one bank active - read - precharge current cke: high; external clock: on; tck, nrc, nras, nrcd, cl : see see the table of timings used for idd and iddq ; bl: 8 (1,7) ; al: 0; ?? : high between act, rd and pre; command, addr ess, bank address inputs, data io: partially toggling; bank activity: cycling with one bank active at a time: 0,0,1,1,2,2,...; output buffer and rtt: enabled in mode registers (2) ; odt signal: stable at 0; idd2n precharge standby current cke : high; exte rnal clock: on; tck, cl : see the table of timings used for idd and iddq ; bl: 8 (1) ; al: 0; ?? : stable at 1; command, address, bank address inputs: partially toggling; data io: mid - level; dm :stable at 0; bank activity: all banks closed; output buffer and rtt: enabled in mode registers (2) ; odt signal: stable at 0; idd2p(0) precharge power - do wn current slow exit cke: low; external clock: on; tck, cl : see the table of timings used for idd and iddq ; bl: 8 (1) ; al: 0; ?? : stable at 1; ddr3 (l) 2 gb sdram nt5c b( c ) 256 m8 f n / nt5cb(c) 128 m16 f p version 1. 6 126 nanya technology cooperation ? 0 4 / 201 4 all rights reserved. command, address, bank address inputs: stable at 0; data io: mid - level; dm :stable at 0 ; bank activity: all b anks closed; output buffer and rtt: enabled in mode registers (2) ; odt signal: stable at 0; pecharge power down mode : slow exit (3) idd2p(1) precharge power - down current fast exit cke: low; external clock: on; tck, cl : see the table of timings used for i dd and iddq ; bl: 8 (1) ; al: 0; ?? : stable at 1; command, address, bank address inputs: stable at 0; data io: mid - level; dm :stable at 0 ; bank activity: all banks closed; output buffer and rtt: enabled in mode registers (2) ; odt signal: stable at 0; pecharge power down mode : fast exi t (3) idd2q precharge quiet standby current cke : high; external clock: on; tck, cl : see the table of timings used for idd and iddq ; bl: 8 (1) ; al: 0; ?? : stable at 1; command, address, bank address inputs: stable at 0; data io: mid - level; dm :stable at 0 ; bank activity: all banks closed; output buffer and rtt: enabled in mode registers (2) ; odt signal: stable at 0 idd3n active standby current cke : high; external clock: on; tck, cl : see the table of timings used for idd and iddq ; bl: 8 (1) ; al: 0; ?? : stable at 1; command, address, bank address inputs: partially toggling; data io: mid - level; dm :stable at 0; ddr3 (l) 2 gb sdram nt5c b( c ) 256 m8 f n / nt5cb(c) 128 m16 f p version 1. 6 127 nanya technology cooperation ? 0 4 / 201 4 all rights reserved. bank activity: all banks open; output buffer and rtt: enabled in mode registers (2) ; odt signal: stable at 0; idd3p active power - down current cke : low; external clock: on; tck, cl : see the table of timings used for idd and iddq ; bl: 8 (1) ; al: 0; ?? : stable at 1; command, address, bank address inputs: stable at 0; data io: mid - level; dm :stable at 0; bank activity: all banks open; output buffer and rtt: enabled in mode registers (2) ; odt signal: stable at 0 idd4r operating burst read current cke : high; external clock: on; tck, cl : see the table of timings used for idd and iddq ; bl: 8 (1,7) ; al: 0; ?? : high between rd; command, address, bank address inputs: partially toggling; data io: seamless read data burst with different data between one bu rst and the next one; dm :stable at 0; bank activity: all banks open, rd commands cycling through banks: 0,0,1,1,2,2,...; output buffer and rtt: enabled in mode registers (2) ; odt signal: stable at 0; idd4w operating burst write current cke: high; extern al clock: on; tck, cl : see the table of timings used for idd and iddq ; bl: 8 (1) ; al: 0; ?? : high between wr; command, address, bank address inputs: partially toggling; data io: seamless write data burst with different data between one burst and the next one ; dm: stable at 0; bank activity: all banks open, wr commands cycling through banks: 0,0,1,1,2,2,...; output buffer and rtt: enabled in mode registers (2) ; odt signal: stable at high; ddr3 (l) 2 gb sdram nt5c b( c ) 256 m8 f n / nt5cb(c) 128 m16 f p version 1. 6 128 nanya technology cooperation ? 0 4 / 201 4 all rights reserved. idd5b burst refresh current cke: high; external clock: on; tck, cl, nrfc : see the table of timings used for idd and iddq ; bl: 8 (1) ; al: 0; ?? : high betw een ref; command, address, bank address inputs: partially toggling; data io: mid - level; dm :stable at 0; bank activity: ref command every nrfc; output buffer and rtt: enabled in mode registers (2) ; odt signal: stable at 0; idd6 self refresh current: no rmal temperature range t case : 0 - 85c; auto self - refresh (asr) : disabled (4) ; self - refresh temperature range (srt): normal (5) ; cke: low; external clock: off; ck and ?? : low; cl : see the table of timings used for idd and iddq ; bl: 8 (1) ; al: 0; ?? , command, address, bank address, data io: mid - level; dm :stable at 0; bank activity: self - refresh operation; output buffer and rtt: enabled in mode registers (2) ; odt signal: mid - level idd6et self - refresh current: extended temperature range (optional) (6) t case : 0 - 95c; auto self - refresh (asr) : disabled (4) ; self - refresh temperature range (srt): extended (5) ; cke: low; external clock: off; ck and ?? : low; cl : see the table o f timings used for idd and iddq ; bl: 8 (1) ; al: 0; ?? , command, address, bank address, data io: mid - level; dm :stable at 0; bank activity: extended temperature self - refresh operation; output buffer and rtt: enabled in mode registers (2) ; odt signal: mid - leve l idd 6tc auto self - refresh current (optional) (6) t case : 0 - 95c; auto self - refresh (asr) : enabled (4) ; ddr3 (l) 2 gb sdram nt5c b( c ) 256 m8 f n / nt5cb(c) 128 m16 f p version 1. 6 129 nanya technology cooperation ? 0 4 / 201 4 all rights reserved. self - refresh temperature range (srt): normal (5) ; cke: low; external clock: off; ck and ?? : low; cl : see the table of timings used for idd and iddq ; bl : 8 (1) ; al: 0; ?? , command, address, bank address, data io: mid - level; dm :stable at 0; bank activity: auto self - refresh operation; output buffer and rtt: enabled in mode registers (2) ; odt signal: midlevel idd 7 operating bank interleave read current cke : high; external clock: on; tck, nrc, nras, nrcd, nrrd, nfaw, cl : see the table of timings used for idd and iddq ; bl: 8 (1,7) ; al: cl - 1; ?? : high between act and rda; command, address, bank address inputs: partially toggling; data io: read data bursts wit h different data between one burst and the next one; dm :stable at 0; bank activity: two times interleaved cycling through banks (0, 1, ...7) with different addressing; output buffer and rtt: enabled in mode registers (2) ; odt signal: stable at 0; idd8 reset low current reset: low; external clock: off; ck and ?? : low; cke: floating; ?? , command, address,bank address, data io: floating; odt signal: floating reset low current reading is valid once power is stable and reset has been low for at least 1ms. note 1. burst length: bl8 fixed by mrs: set mr0 a[1,0]=00 b note 2. output buffer enable: set mr1 a[12] = 0b; set mr1 a[5,1] = 01b; rtt_nom enable: set mr1 a[9,6,2] = 011b; rtt_wr enable: set mr2 a[10,9] = 10b note 3. pecharge power down mode: set mr0 a12=0b for slow exit or mr0 a12=1b for fast exit note 4. auto self - refresh (asr): set mr2 a6 = 0b to disable or 1b to enable feature note 5. self - refresh temperature range (srt): set mr2 a7=0b for normal or 1b for extended temperature range note 6. refer to dram supplier data sheet and/or dimm spd to determine if opt ional features or requirements are supported by ddr3 sdram device note 7. read burst type: nibble sequential, set mr0 a[3] = 0b ddr3 (l) 2 gb sdram nt5c b( c ) 256 m8 f n / nt5cb(c) 128 m16 f p version 1. 6 130 nanya technology cooperation ? 0 4 / 201 4 all rights reserved. idd0 measurement - loop pattern ddr3 (l) 2 gb sdram nt5c b( c ) 256 m8 f n / nt5cb(c) 128 m16 f p version 1. 6 131 nanya technology cooperation ? 0 4 / 201 4 all rights reserved. idd 1 measurement - loop pattern ddr3 (l) 2 gb sdram nt5c b( c ) 256 m8 f n / nt5cb(c) 128 m16 f p version 1. 6 132 nanya technology cooperation ? 0 4 / 201 4 all rights reserved. idd 2n and idd3n measurement - loop patte rn ddr3 (l) 2 gb sdram nt5c b( c ) 256 m8 f n / nt5cb(c) 128 m16 f p version 1. 6 133 nanya technology cooperation ? 0 4 / 201 4 all rights reserved. idd4r and iddq4r measurement - loop pattern idd4 w measurement - loop pattern ddr3 (l) 2 gb sdram nt5c b( c ) 256 m8 f n / nt5cb(c) 128 m16 f p version 1. 6 134 nanya technology cooperation ? 0 4 / 201 4 all rights reserved. idd5b measurement - loop pattern ddr3 (l) 2 gb sdram nt5c b( c ) 256 m8 f n / nt5cb(c) 128 m16 f p version 1. 6 135 nanya technology cooperation ? 0 4 / 201 4 all rights reserved. idd7 measurement - loop pattern ddr3 (l) 2 gb sdram nt5c b( c ) 256 m8 f n / nt5cb(c) 128 m16 f p version 1. 6 136 nanya technology cooperation ? 0 4 / 201 4 all rights reserved. fundamental ac specifications C operating frequency ddr3 - 2133 speed bins ddr3 - 2133 14 - 14 - 14 unit pa rameter min max tck (avg) cl5 cwl5 reserved ns cwl6/7/8/9/10 reserved ns cl6 cwl5 2.5 3.3 ns cwl6 reserved ns cwl7/8/9/10 reserved ns cl7 cwl5 reserved ns cwl6 1.875 < 2.5 ns cwl7 reserved ns cwl8/9/10 reserved ns cl8 cwl5 reserve d ns cwl6 1.875 < 2.5 ns cwl7 reserved ns cwl8/9/10 reserved ns cl9 cwl5/6 reserved ns cwl7 1.5 < 1.875 ns cwl8 reserved ns cwl9/10 reserved ns cl10 cwl5/6 reserved ns cwl7 1.5 < 1.875 ns cwl8 reserved ns cwl9 reserved ns cwl10 reserved ns cl11 cwl5/6/7 reserved ns cwl8 1.25 < 1.5 ns cwl9 reserved ns cwl10 reserved ns tck (avg) cl12 cwl5/6/7/8 reserved ns cwl9 reserved ns cwl10 reserved ns cl13 cwl5/6/7/8 reserved ns cwl9 1.07 < 1.25 ns cwl10 reser ved ns cl14 cwl5/6/7/8/9 reserved ns cwl10 0.938 < 1.07 ns supported cl 5,6,7,8,9,10,11,12,13,14 nck supported cwl 5,6,7,8,9,10 nck ddr3 (l) 2 gb sdram nt5c b( c ) 256 m8 f n / nt5cb(c) 128 m16 f p version 1. 6 137 nanya technology cooperation ? 0 4 / 201 4 all rights reserved. fundamental ac specifications C operating frequency ddr3 - 1866 and ddr3l - 1866 speed bins ddr3 (l) - 1866 12 - 12 - 12 ddr3 ( l) - 1866 13 - 13 - 13 unit parameter m in m ax m in m ax tck (avg) cl5 cwl5 reserved reserved ns cwl6/7/8/9 reserved reserved ns cl6 cwl5 2.5 3.3 2.5 3.3 ns cwl6 reserved reserved ns cwl7/8/9 reserved reserved ns cl7 cwl5 reserved reserved ns cwl 6 1.875 < 2.5 1.875 < 2.5 ns cwl7/8/9 reserved reserved ns cl8 cwl5 reserved reserved ns cwl6 1.875 < 2.5 1.875 < 2.5 ns cwl7 reserved reserved ns cwl8 /9 reserved reserved ns cl9 cwl5/6 reserved reserved ns cwl7 1.5 < 1.875 1.5 < 1.875 n s cwl8 reserved reserved ns cwl9 reserved reserved ns cl10 cwl5/6 reserved reserved ns cwl7 1.5 < 1.875 1.5 < 1.875 ns cwl8 reserved reserved ns cl11 cwl5/6/7 reserved reserved ns cwl8 1.25 < 1.5 1.25 < 1.5 ns cwl9 reserved reserved n s cl12 cwl5/6/7/8 reserved reserved ns cwl9 1.07 < 1.25 reserved ns cl13 cwl5/6/7/8 reserved reserved ns cwl9 1.07 < 1.25 1.07 < 1.25 ns supported cl 6,7,8,9,10,11,12,13 6,7,8,9,10,11,13 nck supported cwl 5, 6, 7, 8, 9 5, 6, 7, 8, 9 nck ddr3 (l) 2 gb sdram nt5c b( c ) 256 m8 f n / nt5cb(c) 128 m16 f p version 1. 6 138 nanya technology cooperation ? 0 4 / 201 4 all rights reserved. fund amental ac specifications C operating frequency ddr3 - 1600 and ddr3l - 1600 speed bins ddr3 (l) - 1600 11 - 11 - 11 unit parameter m in m ax tck (avg) cl5 cwl5 3.0 3.3 ns cwl6/7/8 reserved ns cl6 cwl5 2.5 3.3 ns cwl6 reserved ns cwl7/8 reserved ns cl7 cwl5 reserved ns cwl6 1.875 < 2.5 ns cwl7 reserved ns cwl8 reserved ns cl8 cwl5 reserved ns cwl6 1.875 < 2.5 ns cwl7 reserved ns cwl8 reserved ns cl9 cwl5/6 reserved ns cwl7 1.5 <1.875 ns cwl8 reserved ns cl10 cwl5/6 reserved ns cwl7 1.5 < 1.875 ns cwl8 reserved ns cl11 cwl5/6/7 reserved ns cwl8 1.25 <1.5 ns supported cl 5, 6, 7, 8, 9, 10, 11 nck supported cwl 5, 6, 7, 8 nck ddr3 (l) 2 gb sdram nt5c b( c ) 256 m8 f n / nt5cb(c) 128 m16 f p version 1. 6 139 nanya technology cooperation ? 0 4 / 201 4 all rights reserved. fundamental ac specifications C operating frequency ddr3 - 1333 and ddr3l - 1333 speed bins ddr3(l) - 1333 9 - 9 - 9 ddr3 (l) - 1333 10 - 10 - 10 unit parameter m in m ax m in m ax tck (avg ) cl5 cwl5 3.0 3.3 3.0 3.3 ns cwl6 /7 reserved reserved ns cl6 cwl5 2.5 3.3 2.5 3.3 ns cwl6 reserved reserved ns cwl7 reserved reserved ns cl7 cwl5 reserved res erved ns cwl6 1.875 < 2.5 reserved ns cwl7 reserved reserved ns cl8 cwl5 reserved reserved ns cwl6 1.875 < 2.5 1.875 < 2.5 ns cwl 7 reserved reserved ns cl9 cwl5/6 reserved reserved ns cwl7 1.5 < 1.875 reserved ns cl10 cwl5/6 reserved r eserved ns cwl7 1.5 < 1.875 1.5 < 1.875 ns supported cl 5, 6, 7, 8, 9, 10 5, 6, 8, 10 nck supported cwl 5, 6, 7 5, 6, 7 nck ddr3 (l) 2 gb sdram nt5c b( c ) 256 m8 f n / nt5cb(c) 128 m16 f p version 1. 6 140 nanya technology cooperation ? 0 4 / 201 4 all rights reserved. fundamental ac specifications C operating frequency ddr3 - 1066 and ddr3l - 1066 speed bins ddr3(l) - 1066 7 - 7 - 7 ddr3(l) - 1066 8 - 8 - 8 unit parameter m in m ax m in m ax tck (avg) cl5 cwl5 3.0 3.3 3.0 3.3 ns cwl6 reserved reserved ns cl6 cwl5 2.5 3.3 2.5 3.3 ns cwl6 reserved reserved ns cl7 cwl5 reserved reserved ns cwl6 1.875 < 2.5 reserved ns cl8 cwl5 reserved reserved n s cwl6 1.875 < 2.5 1.875 < 2.5 ns supported cl 5, 6, 7, 8 5, 6, 8 nck supported cwl 5, 6 5, 6 nck ddr3 - 800 and ddr3l - 800 speed bins ddr3(l) - 800 5 - 5 - 5 ddr3(l) - 800 6 - 6 - 6 unit parameter m in m ax m in m ax tck (avg) cl5 cwl5 2.5 3.3 3.0 3.3 ns cl6 cw l5 2.5 3.3 2.5 3.3 ns supported cl 5, 6 5, 6 nck supported cwl 5 5 nck fundamental ac specifications notes note 1. the cl setting and cwl setting result in tck(avg).min and tck(avg).max requirements. when making a selection of tck(avg), both need to b e fulfilled: requirements from cl setting as well as requirements from cwl setting. note 2. tck(avg).min limits: since cas latency is not purely analog - data and strobe output are synchronized by the dll - all possible intermediate frequencies may not be guaranteed. an application should use the next smaller jedec standard tck(avg) value (3.0, 2.5, 1.875, 1.5, 1.25, 1.07, or 0.938 ns) when calculating cl [nck] = taa [ns] / tck(avg) [ns], rounding up to the next supported cl, where tck(avg) = 3.0 ns shoul d only be used for cl = 5 calculation. note 3. tck(avg).max limits: calculate tck(avg) = taa.max / cl selected and round the resulting tck(avg) down to the next valid speed bin (i.e. 3.3ns or 2.5ns or 1.875 ns or 1.5 ns or 1.25 ns or 1.07 ns or 0.938 ns). this result is tck(avg).max corresponding to cl selected. note 4. reserved settings are not allowed. user must program a different value. note 5. optional settings allow certain devices in the industry to support this setting, however, it is not a mand atory feature. refer to ddr3 (l) 2 gb sdram nt5c b( c ) 256 m8 f n / nt5cb(c) 128 m16 f p version 1. 6 141 nanya technology cooperation ? 0 4 / 201 4 all rights reserved. suppliers data sheet and/or the dimm spd information if and how this setting is supported. note 6. any ddr3 - 1066 speed bin also supports functional operation at lower frequencies as shown in the table which are not subject to produ ction tests but verified by design/characterization. note 7. any ddr3 - 1333 speed bin also supports functional operation at lower frequencies as shown in the table which are not subject to production tests but verified by design/characterization. note 8. an y ddr3 - 1600 speed bin also supports functional operation at lower frequencies as shown in the table which are not subject to production tests but verified by design/characterization. note 9. any ddr3 - 1866 speed bin also supports functional operation at low er frequencies as shown in the table which are not subject to production tests but verified by design/characterization. note 10.any ddr3 - 2133 speed bin also supports functional operation at lower frequencies as shown in the table which are not subject to p roduction tests but verified by design/characterization. note 11.for devices supporting optional down binning to cl=7 and cl=9, taa/trcd/trpmin must be 13.125 ns. spd settings must be programmed to match. for example, ddr3 - 1333 (9 - 9 - 9) devices supporting do wn binning to ddr3 - 1066 ( 7 - 7 - 7 ) should program 13.125 ns in spd bytes for taamin (byte 16), trcdmin (byte 18), and trpmin (byte 20). ddr3 - 1600 ( 11 - 11 - 11 ) devices supporting down binning to ddr3 - 1333 (9 - 9 - 9) or ddr3 - 1066 (7 - 7 - 7) should program 13.125 ns in spd bytes for taamin (byte16), trcdmin (byte 18), and trpmin (byte 20). once trp (byte 20) is programmed to 13.125ns, trcmin (byte 21,23) also should be programmed accodingly. for example, 49.125ns (trasmin + trpmin = 36 ns + 13.125 ns) for ddr3 - 1333 (9 - 9 - 9) an d 48.125ns (trasmin + trpmin = 35 ns + 13.125 ns) for ddr3 - 1600 ( 11 - 11 - 11 ) . note 12.ddr3 800 ac timing apply if dram operates at lower than 800 mt/s data rate. note 13.for cl5 support, refer to dimm spd information. dram is required to support cl5. cl5 is n ot mandatory in spd coding. note 14.for devices supporting optional down binning to cl=11, cl=9 and cl=7, taa/trcd/trpmin must be 13.125ns. spd setting must be programed to match. for example, ddr3 - 1866 ( 13 - 13 - 13 ) devices supporting down binning to ddr3 - 160 0 ( 11 - 11 - 11 ) or ddr3 - 1333 (9 - 9 - 9) or 1066 ( 7 - 7 - 7 ) should program 13.125ns in spd bytes for taamin(byte16), trcdmin(byte18) and trpmin (byte20). once trp (byte 20) is programmed to 13.125ns, trcmin (byte 21,23) also should be programmed accordingly. for exampl e, 47.125ns (trasmin + trpmin = 34 ns+ 13.125 ns) ddr3 (l) 2 gb sdram nt5c b( c ) 256 m8 f n / nt5cb(c) 128 m16 f p version 1. 6 142 nanya technology cooperation ? 0 4 / 201 4 all rights reserved. electrical characteristics & ac timing timing parameters for ddr3 (l) - 800 , ddr3 (l) - 1066 , and ddr3 (l) - 1333 parameter symbol ddr3 (l) - 800 ddr3 (l) - 1 0 66 ddr3(l) - 1333 unit min. max. min. max. min. max. clo ck timing minimum clock cycle time (dll off mode) t ck ( dll_off ) 8 - 8 - 8 - ns average clock period t ck ( avg ) refer to fundamental ac specifications ps average high pulse width t ch ( avg ) 0.47 0.53 0.47 0.53 0.47 0.53 tck (avg) average low pulse width t c l ( avg ) 0.47 0.53 0.47 0.53 0.47 0.53 tck(avg) absolute clock period t ck ( abs ) min.: tck (avg)min + tjit (per)min max.: tck (avg)max + tjit (per)max ps absolute clock high pulse width t ch ( abs ) 0.43 - 0.43 - 0.43 - tck(avg) absolute clock low pulse width t cl ( abs ) 0.43 - 0.43 - 0.43 - tck(avg) clock period jitter jit( per ) - 10 0 10 0 - 9 0 9 0 - 80 80 ps clock period jitter during dll locking period jit( per , lck ) - 9 0 9 0 - 8 0 8 0 - 70 70 ps cycle to cycle period jitter t jit ( cc ) 20 0 1 8 0 160 ps cycle to cycle period jit ter during dll locking period jit( cc , lck ) 1 8 0 1 6 0 140 ps duty cycle jitter t jit ( duty ) - - - - - - ps cumulative error across n = 2 , 14 . . . 49, 50 cycles t err ( nper ) terr (nper) min = (1 + 0.68ln(n)) * tjit (per)min terr (nper) max = (1 + 0.68ln(n)) * tji t (per)max ps data timing dqs, ??? to dq skew, per group, per access t dqsq - 200 - 150 - 125 ps dq output hold time from dqs, ??? t qh 0.38 - 0.38 - 0.38 - tck(avg) dq low - impedance time from ck, ?? t lz (dq) - 800 400 - 60 0 300 - 500 250 ps dq high impedan ce time from ck, ?? t hz (dq) - 400 - 300 - 250 ps data setup time to dqs, ??? referenced to vih(ac) / vil(ac) levels t ds ( base ) ddr3 - ac175 75 - 25 - - - ps t ds ( base ) ddr3 - ac150 125 - 75 - 30 - ps t ds ( base ) ddr3l - ac1 60 90 - 40 - - - ps t ds ( base ) ddr3l - ac1 3 5 140 - 90 - 45 - ps data hold time from dqs, ??? referenced to vih(dc) / vil(dc) levels t dh ( base ) ddr3 - dc100 150 - 100 - 65 - ps t dh ( base ) ddr3l - dc 9 0 160 - 110 - 75 - ps dq and dm input pulse width for each input t dipw 60 0 - 49 0 - 400 - ps data strobe timing dqs, ??? differential read preamble t rpre 0.9 note 19 0.9 note 19 0.9 note 19 tck(avg) dqs, ??? differential read postamble t rpst 0.3 note 11 0.3 note 11 0.3 note 11 tck(avg) dqs, ??? differential output high time t qsh 0. 38 - 0. 38 - 0.4 - tck(avg) dqs, ??? differential output low time t qsl 0. 38 - 0. 38 - 0.4 - tck(avg) dqs, ??? differential write preamble t wpre 0.9 - 0.9 - 0.9 - tck(avg) dqs, ??? differential write postamble t wpst 0.3 - 0.3 - 0.3 - tck(avg) dqs, ??? rising edge output ac cess time from rising ck, ?? t dqsck - 400 400 - 300 300 - 255 255 ps dqs and ??? low - impedance time (referenced from rl C 1) t lz (dqs) - 80 0 400 - 60 0 300 - 500 250 ps dqs and ??? high - impedance time (referenced from rl + bl/2) t hz (dqs) - 400 - 300 - 250 ps dqs, ??? differential input low pulse width t dqsl 0.45 0.55 0.45 0.55 0.45 0.55 tck(avg) dqs, ??? differential input high pulse width t dqsh 0.45 0.55 0.45 0.55 0.45 0.55 tck(avg) dqs, ??? rising edge to ck, ?? rising edge t dqss - 0.2 5 0.2 5 - 0.2 5 0.2 5 - 0.2 5 0.2 5 tck(avg) dqs, ??? falling edge setup time to ck, ?? rising edge t dss 0. 2 - 0. 2 - 0. 2 - tck(avg) dqs, ??? falling edge hold time from ck, ?? rising edge t dsh 0. 2 - 0. 2 - 0. 2 - tck(avg) ddr3 (l) 2 gb sdram nt5c b( c ) 256 m8 f n / nt5cb(c) 128 m16 f p version 1. 6 143 nanya technology cooperation ? 0 4 / 201 4 all rights reserved. command and address timing dll locking time t dllk 512 - 512 - 512 - nck internal read command to precharge command delay t rtp trtpmin.: max(4 tck , 7.5ns) trtpmax.: - delay from start of internal write transaction to internal read command t wtr twtrmin.: max(4 tck , 7.5ns) twtrmax.: - write recovery time t wr 15 - 15 - 15 - ns mode register set command cycle time t mrd 4 - 4 - 4 - nck mode register set command update delay t mod tmodmin.: max(12 tck , 15ns) tmodmax.: act to internal read or write delay time trcd refer to fundamental ac specifications pre command period trp act to act or ref command period trc active to precharge command period t ras ?a? to ?a? command delay t ccd 4 - 4 - 4 - nck auto precharge write recovery + precharge time t dal ( min ) wr + roundup( trp / tck (avg)) nck multi - purpose register recovery time t mprr 1 - 1 - 1 - nck active to active command period ( 1kb page size ) t rrd max(4 t ck,1 0ns) - max(4 t ck,7.5n s) - max(4 t ck ,6ns) - active to active command period ( 2kb page size ) t rrd ma x(4 t ck,1 0ns) - max(4 t ck,10n s) - max(4 t ck ,7.5ns) - four activate window ( 1kb page size ) t faw 4 0 - 37.5 - 30 - ns four activate window ( 2kb page size ) t faw 50 - 50 - 45 - ns command and address setup time to ck, ?? referenced to vih(ac) / vil(ac) levels t is ( base ) ddr3 - ac175 200 - 125 - 65 - ps t i s ( base ) ddr3 - ac150 350 - 275 - 190 - ps t is ( base ) ddr3l - ac160 215 - 140 - 80 - ps t i s ( base ) ddr3l - ac135 365 - 290 - 205 - ps command and address hold time from ck, ?? referenced to vih( d c) / vil( d c) levels t i h ( base ) ddr3 - dc100 275 - 200 - 140 - ps t i h ( base ) ddr3l - dc 9 0 285 - 210 - 150 - ps control and address input pulse width for each input t ipw 900 - 780 - 620 - ps calibration timing power - up and reset calibrat ion time t zq init tzq init min: max(512 t ck, 640ns) tzq initmax: - normal operation full calibration time t zq oper tzq oper min: max( 256t ck, 32 0ns) tzq opermax: - normal operation short calibration time t zqcs tzqcs min: max( 64 tck , 8 0ns) tzqcsmax: - reset timi ng exit reset from cke high to a valid command t xpr txprmin.: max(5 tck , trfc (min) + 10ns) txprmax.: - self refresh timings exit self refresh to commands not requiring a locked dll t xs txsmin.: max(5 tck , trfc (min) + 10ns) txsmax.: - exit self refresh to commands requiring a locked dll t xsdll txsdllmin.: tdllk (min) txsdllmax.: - nck minimum cke low width for self refresh entry to exit timing t ckesr tckesrmin.: tcke (min) + 1 tck tckesrmax.: - valid clock requirement after self refresh entry (sre) or power - down entry (pde) t cksre tcksremin.: max(5 tck , 10 ns) tcksremax.: - valid clock requirement before self refresh exit (srx) or power - down exit (pdx) or reset exit t cksrx tcksrxmin.: max(5 tck , 10 ns) tcksrxmax.: - ddr3 (l) 2 gb sdram nt5c b( c ) 256 m8 f n / nt5cb(c) 128 m16 f p version 1. 6 144 nanya technology cooperation ? 0 4 / 201 4 all rights reserved. power down timings exit power down with dll on to any valid command; exit precharge power down with dll frozen to commands not requ iring a locked dll t xp max(3 t ck,7. 5ns) - max(3 t ck,7.5n s) - max(3 t ck ,6ns) - cke minimum pulse width t cke max(3 t ck7. 5ns) - max(3 t ck,5.62 5ns) - max(3 t ck ,5.625ns) - exit precharge power down with dll frozen to commands requiring a locked dll t xpdll txpdllm in.: max(10 tck , 24ns) txpdllmax.: - command pass disable delay t cpded tcpdedmin.: 1 tcpdedmin.: - nck power down entry to exit timing t pd tpdmin.: tcke (min) tpdmax.: 9* trefi timing of act command to power down entry t actpden tactpdenmin.: 1 tactpdenm ax.: - nck timing of pre or prea command to power down entry t prpden tprpdenmin.: 1 tprpdenmax.: - nck timing of rd/rda command to power down entry t rdpden trdpdenmin.: rl+4+1 trdpdenmax.: - nck timing of wr command to power down entry (bl8otf, bl8mrs, bc4otf) t wrpden twrpdenmin.: wl + 4 + ( twr / tck (avg)) twrpdenmax.: - nck timing of wra command to power down entry (bl8otf, bl8mrs, bc4otf) t wrapden twrapdenmin.: wl+4+wr+1 twrapdenmax.: - nck timing of wr command to power down entry (bc4mrs) t wrpden t wrpdenmin.: wl + 2 + ( twr / tck (avg)) twrpdenmax.: - nck timing of wra command to power down entry (bc4mrs) t wrapden twrapdenmin.: wl + 2 +wr + 1 twrapdenmax.: - nck timing of ref command to power down entry t refpden trefpdenmin.: 1 trefpdenmax.: - nck timing of mrs command to power down entry t mrspden tmrspdenmin.: tmod (min) tmrspdenmax.: - odt timings odt turn on latency odtlon wl - 2=cwl+al - 2 nck odt turn off latency odtloff wl - 2=cwl+al - 2 nck odt high time without write command or with write comm and and bc4 odth4 odth4min.: 4 odth4max.: - nck odt high time with write command and bl8 odth8 odth8min.: 6 odth8max.: - nck asynchronous rtt turn - on delay (power - down with dll frozen) t aonpd 2 8.5 2 8.5 2 8.5 ns asynchronous rtt turn - off delay (power - down with dll frozen) t aofpd 2 8.5 2 8.5 2 8.5 ns rtt turn - on t aon - 400 400 - 300 300 - 250 250 ps rtt_nom and rtt_wr turn - off time from odtloff reference taof 0.3 0.7 0.3 0.7 0.3 0.7 tck(avg) rtt dynamic change skew t adc 0.3 0.7 0.3 0.7 0.3 0.7 tck(avg ) write leveling timings first dqs/ ??? rising edge after write leveling mode is programmed t wlmrd 40 - 40 - 40 - nck dqs/ ??? delay after write leveling mode is programmed t wldqsen 25 - 25 - 25 - nck write leveling setup time from rising ck, ?? crossin g to rising dqs, ??? crossing t wls 325 - 245 - 195 - ps write leveling hold time from rising dqs, ??? crossing to rising ck, ?? crossing t wlh 325 - 245 - 195 - ps write leveling output delay t wlo 0 9 0 9 0 9 ns write leveling output error t wloe 0 2 0 2 0 2 ns ddr3 (l) 2 gb sdram nt5c b( c ) 256 m8 f n / nt5cb(c) 128 m16 f p version 1. 6 145 nanya technology cooperation ? 0 4 / 201 4 all rights reserved. timing parameters for ddr3 (l) - 16 00 , ddr3 (l) - 1 8 66 , and ddr3 (l) - 21 33 parameter symbol ddr3 (l) - 1600 ddr3 (l) - 1 8 66 ddr3(l) - 2133 unit min. max. min. max. min. max. clock timing minimum clock cycle time (dll off mode) t ck ( dll_off ) 8 - 8 - 8 - ns average clock period t ck ( avg ) refer to fundamental ac specifications average high pulse width t ch ( avg ) 0.47 0.53 0.47 0.53 0.47 0.53 tck (avg) average low pulse width t cl ( avg ) 0.47 0.53 0.47 0.53 0.47 0.53 tck (avg) absolute clock period t ck ( abs ) min .: tck(avg)min + tjit(per)min max.: tck(avg)max + tjit(per)max absolute clock high pulse width t ch ( abs ) 0.43 - 0.43 - 0.43 - tck (avg) absolute clock low pulse width t cl ( abs ) 0.43 - 0.43 - 0.43 - tck(avg) clock period jitter jit( per ) - 7 0 7 0 - 6 0 6 0 - 50 5 0 ps clock period jitter during dll locking period jit( per , lck ) - 6 0 6 0 - 5 0 5 0 - 40 40 ps cycle to cycle period jitter t jit ( cc ) 1 4 0 1 2 0 100 cycle to cycle period jitter during dll locking period jit( cc , lck ) 1 2 0 1 0 0 80 duty cycle jitter t jit ( duty ) - - - - - - ps cumulative error across n = 2 , 14 . . . 49, 50 cycles t err ( nper ) terr (nper) min = (1 + 0.68ln(n)) * tjit (per)min terr (nper) max = (1 + 0.68ln(n)) * tjit (per)max ps data timing dqs, ??? to dq skew, per group, per access t dqsq - 100 - 85 - 7 5 ps dq output hold time from dqs, ??? t qh 0.38 - 0.38 - 0.38 - tck (avg) dq low - impedance time from ck, ?? t lz (dq) - 450 2 25 - 39 0 195 - 360 180 ps dq high impedance time from ck, ?? t hz (dq) - 2 25 - 195 - 180 ps data setup time to dqs, ??? referenced to vih(ac) / vil(ac) levels t ds ( base ) ddr3 - 1600( ac 175 ) ddr3 - 1866/21 33(ac150) - - - - - - ps t ds ( base ) ddr3 - 1600( ac 150 ) ddr3 - 1866/21 33(ac135) 10 - 68 - 53 - ps t ds ( base ) ddr3l - 1600( ac1 35) , sr= 1v/ns ddr3l - 1866( ac1 30),sr=2v/ns 25 - 70 - - - ps data hold tim e from dqs, ??? referenced to vih(dc) / vil(dc) levels t dh ( base ) dc100 45 - - - - - ps tdh(base) dc90 ddr3l - 1600( sr =1v/ns ) ddr3l - 1 866 ( sr = 2 v/ns ) 55 - 75 - - - ps dq and dm input pulse width for each input t dipw 36 0 - 3 2 0 - 280 - ps data strobe timing dqs, ??? diff erential read preamble t rpre 0.9 note 19 0.9 note 19 0.9 note 19 tck(avg) dqs, ??? differential read postamble t rpst 0.3 note 11 0.3 note 11 0.3 note 11 tck(avg) dqs, ??? differential output high time t qsh 0.4 - 0.4 - 0.4 - tck(avg) dqs, ??? differentia l output low time t qsl 0.4 - 0.4 - 0.4 - tck(avg) dqs, ??? differential write preamble t wpre 0.9 - 0.9 - 0.9 - tck(avg) dqs, ??? differential write postamble t wpst 0.3 - 0.3 - 0.3 - tck(avg) dqs, ??? rising edge output access time from rising ck, ?? t dq sck - 2 2 5 2 2 5 - 195 19 5 - 180 180 ps dqs and ??? low - impedance time (referenced from rl C 1) t lz (dqs) - 4 50 2 25 - 39 0 195 - 360 180 ps dqs and ??? high - impedance time t hz (dqs) - 2 25 - 195 - 180 ps ddr3 (l) 2 gb sdram nt5c b( c ) 256 m8 f n / nt5cb(c) 128 m16 f p version 1. 6 146 nanya technology cooperation ? 0 4 / 201 4 all rights reserved. (referenced from rl + bl/2) dqs, ??? differential input low pulse width t dqsl 0.45 0.55 0.45 0.55 0.45 0.55 tck(avg) dqs, ??? differential input high pulse width t dqsh 0.45 0.55 0.45 0.55 0.45 0.55 tck(avg) dqs, ??? rising edge to ck, ?? rising edge t dqss - 0.2 7 0.2 7 - 0.27 0.27 - 0.27 0.27 tck(avg) dqs, ??? fallin g edge setup time to ck, ?? rising edge t dss 0. 18 - 0.18 - 0.18 - tck(avg) dqs, ??? falling edge hold time from ck, ?? rising edge t dsh 0. 18 - 0.18 - 0.18 - tck(avg) command and address timing dll locking time t dllk 512 - 512 - 512 - nck internal rea d command to precharge command delay t rtp trtpmin.: max(4 tck , 7.5ns) trtpmax.: - delay from start of internal write transaction to internal read command t wtr twtrmin.: max(4 tck , 7.5ns) twtrmax.: - write recovery time t wr 15 - 15 - 15 - ns mode regis ter set command cycle time t mrd 4 - 4 - 4 - nck mode register set command update delay t mod tmodmin.: max(12 tck , 15ns) tmodmax.: act to internal read or write delay time trcd refer to fundamental ac specifications pre command period trp act to a ct or ref command period trc active to precharge command period t ras ?a? to ?a? command delay t ccd 4 - 4 - 4 - nck auto precharge write recovery + precharge time t dal ( min ) wr + roundup( trp / tck (avg)) nck multi - purpose register recovery time t mprr 1 - 1 - 1 - nck active to active command period ( 1kb page size ) t rrd max(4 t ck, 6 ns) - max(4 t ck ,5ns) - max(4 t ck , 5 ns) - active to active command period ( 2kb page size ) t rrd max(4 t ck, 7.5 ns) - max(4 t ck , 6 ns) - max(4 t ck , 6 ns) - four activate window ( 1kb page size ) t faw 30 - 27 - 25 - ns four activate window ( 2kb page size ) t faw 4 0 - 35 - 35 - ns command and address setup time to ck, ?? referenced to vih(ac) / vil(ac) levels t is ( base ) ddr3 - 1600(ac 175) ddr3 - 1866/21 33(ac150) 45 - - - - - ps t i s ( base ) ddr3 - 1600(ac 150) ddr3 - 1866/21 33(ac125) 170 - 1 5 0 - 135 - ps t i s ( base ) ddr3l (ac160) 60 - - - - ps t i s ( base ) ddr3l (ac135) 185 - 65 - - - ps t i s ( base ) ddr3l (ac125) - - 150 - - - ps command and address hold time from ck, ?? referenced to vih( d c) / vil( d c) levels t i h ( base ) ddr3 dc100 120 - 1 00 - 95 - ps t i h ( base ) ddr3l dc90 130 - 110 - - - ps control and address input pulse width for each input t ipw 560 - 5 35 - 470 - ps calibration timing power - up and reset calibration time t zq init tzq init min: max(512 t ck, 640ns) tzq initmax: - normal operation full calibration time t zq oper tzq oper min: max( 256t ck, 32 0ns) tzq opermax: - ddr3 (l) 2 gb sdram nt5c b( c ) 256 m8 f n / nt5cb(c) 128 m16 f p version 1. 6 147 nanya technology cooperation ? 0 4 / 201 4 all rights reserved. normal o peration short calibration time t zqcs tzqcs min: max( 64 tck , 8 0ns) tzqcsmax: - reset timing exit reset from cke high to a valid command t xpr txprmin.: max(5 tck , trfc (min) + 10ns) txprmax.: - self refresh timings exit self refresh to commands not requ iring a locked dll t xs txsmin.: max(5 tck , trfc (min) + 10ns) txsmax.: - exit self refresh to commands requiring a locked dll t xsdll txsdllmin.: tdllk (min) txsdllmax.: - nck minimum cke low width for self refresh entry to exit timing t ckesr tckesrmin.: tcke (min) + 1 tck tckesrmax.: - valid clock requirement after self refresh entry (sre) or power - down entry (pde) t cksre tcksremin.: max(5 tck , 10 ns) tcksremax.: - valid clock requirement before self refresh exit (srx) or power - down exit (pdx) or rese t exit t cksrx tcksrxmin.: max(5 tck , 10 ns) tcksrxmax.: - power down timings exit power down with dll on to any valid command; exit precharge power down with dll frozen to commands not requiring a locked dll t xp max(3 t ck, 6 ns) - max(3 t ck , 6 ns) - max(3 t ck , 6ns) - cke minimum pulse width t cke max(3 t ck 5 ns) - max(3 t ck ,5ns) - max(3 t ck ,5ns) - exit precharge power down with dll frozen to commands requiring a locked dll t xpdll txpdllmin.: max(10 tck , 24ns) txpdllmax.: - command pass disable delay t cpded tcpded min.: 1 tcpdedmin.: - nck power down entry to exit timing t pd tpdmin.: tcke (min) tpdmax.: 9* trefi timing of act command to power down entry t actpden tactpdenmin.: 1 tactpdenmax.: - nck timing of pre or prea command to power down entry t prpden tprpdenm in.: 1 tprpdenmax.: - nck timing of rd/rda command to power down entry t rdpden trdpdenmin.: rl+4+1 trdpdenmax.: - nck timing of wr command to power down entry (bl8otf, bl8mrs, bc4otf) t wrpden twrpdenmin.: wl + 4 + ( twr / tck (avg)) twrpdenmax.: - nck tim ing of wra command to power down entry (bl8otf, bl8mrs, bc4otf) t wrapden twrapdenmin.: wl+4+wr+1 twrapdenmax.: - nck timing of wr command to power down entry (bc4mrs) t wrpden twrpdenmin.: wl + 2 + ( twr / tck (avg)) twrpdenmax.: - nck timing of wra comman d to power down entry (bc4mrs) t wrapden twrapdenmin.: wl + 2 +wr + 1 twrapdenmax.: - nck timing of ref command to power down entry t refpden trefpdenmin.: 1 trefpdenmax.: - nck timing of mrs command to power down entry t mrspden tmrspdenmin.: tmod (min) tm rspdenmax.: - odt timings odt turn on latency odtlon wl - 2=cwl+al - 2 nck odt turn off latency odtloff wl - 2=cwl+al - 2 nck odt high time without write command or with write command and bc4 odth4 odth4min.: 4 odth4max.: - nck odt high time with write comm and and bl8 odth8 odth8min.: 6 odth8max.: - nck asynchronous rtt turn - on delay (power - down with dll frozen) t aonpd 2 8.5 2 8.5 2 8.5 ns asynchronous rtt turn - off delay (power - down with dll frozen) t aofpd 2 8.5 2 8.5 2 8.5 ns rtt turn - on t aon - 225 225 - 195 195 - 180 180 ps ddr3 (l) 2 gb sdram nt5c b( c ) 256 m8 f n / nt5cb(c) 128 m16 f p version 1. 6 148 nanya technology cooperation ? 0 4 / 201 4 all rights reserved. rtt_nom and rtt_wr turn - off time from odtloff reference taof 0.3 0.7 0.3 0.7 0.3 0.7 tck(avg) rtt dynamic change skew t adc 0.3 0.7 0.3 0.7 0.3 0.7 tck(avg) write leveling timings first dqs/ ??? rising edge after write leveling mod e is programmed t wlmrd 40 - 40 - 40 - nck dqs/ ??? delay after write leveling mode is programmed t wldqsen 25 - 25 - 25 - nck write leveling setup time from rising ck, ?? crossing to rising dqs, ??? crossing t wls 1 6 5 - 1 40 - 125 - ps write leveling hold t ime from rising dqs, ??? crossing to rising ck, ?? crossing t wlh 1 6 5 - 1 40 - 125 - ps write leveling output delay t wlo 0 7.5 0 7.5 0 7.5 ns write leveling output error t wloe 0 2 0 2 0 2 ns jitter notes note 1 unit tck(avg) represents the actual tck( avg) of the input clock under operation. unit nck represents one clock cycle of the input clock, counting the actual clock edges. ex) tmrd=4 [nck] means; if one mode register set command is regis - tered at tm, anther mode register set command may be regis tered at tm+4, even if (tm+4 - tm) is 4 x tck(avg) + terr(4per), min. note 2 these parameters are measured from a command/address signal (cke, ?? , ra? , ?a? , we , odt, ba0, a0, a1, etc) transition edge to its respective clock signal (ck/ ?? ) crossing. the spec values are not affected by the amount of clock jitter applied (i.e. tjit(per), tjit(cc), etc.), as the setup and hold are relative to the clo ck signal crossing that latches the command/address. that is, these parameters should be met whether clock jitter is present or not. note 3 these parameters are measured from a data strobe signal (dqs(l/u), ????l?u )) crossing to its respective clock signa l (ck, ?? ) crossing. the spec values are not affected by the amount of clock jitter applied (i.e. tjit(per), tjit(cc), etc), as these are relative to the clock signal crossing. that is, these parameters should be met whether clock jitter is present or not. note 4 these parameters are measured from a data signal (dm(l/u), dq(l/u)0, dq(l/u )1, etc.) transition edge to its respective data strobe signal (dqs(l/u), ????l?u? ) crossing. note 5 for these parameters, the ddr3(l) sdram device supports tnparam [nck] = ru{tparam[ns] / tck (avg)[ns]}, which is in clock cycles, assuming all input clock jitter specifications are satisfied. note 6 when the device is operated with input clock jitter, this parameter needs to be derated by the actual terr(mper), act of the inpu t clock, where 2 <= m <=12. (output derating is relative to the sdram input clock.) note 7 when the device is operated with input clock jitter, this parameter needs to be derated by the actual tjit(per),act of the input clock. (output deratings are relativ e to the sdram input clock.) ddr3 (l) 2 gb sdram nt5c b( c ) 256 m8 f n / nt5cb(c) 128 m16 f p version 1. 6 149 nanya technology cooperation ? 0 4 / 201 4 all rights reserved. timing parameter notes 1. actual value dependent upon measurement level definitions which are tbd. 2. commands requiring a locked dll are: read ( and rap) are synchronous odt commands. 3. the max values are system dependent. 4. wr as pro grammed in mode register. 5. value must be rouned - up to next higher integer value. 6. there is no maximum cycle time limit besides the need to satisfy the refresh interval, t refi . 7. for definition of rtt - on time t aon see timing parameters. 8. for definition of rtt - off time t aof see timing parameters. 9. t wr is defined in ns, for calculation of t wrpden it is necessary to round up t wr /t ck to the next integer. 10. wr in clock cycles are programmed in mr0. 11. the maximum read postamble is bounded by t dqsck (min) plus t qsh (min) o n the left side and t hz (dqs)max on the right side. 12. output timing deratings are relative to the sdram input clock. when the device is operated with input clock jitter, this parameter needs to be derated by tbd. 13. value is only valid for ron34. 14. single ended si gnal parameter. 15. t refi depends on t oper . 16. t is (base) and t ih (base) values are for 1v/ns cmd/add single - ended slew rate and 2v/ns ck, ck differential slew rate. note for dq and dm signals, v ref (dc)=vref dq (dc). for input only pins except reset, vref(dc)=vref ca (dc). 17. t ds (base) and t dh (base) values are for 1v/ns dq single - ended slew rate and 2v/ns dqs, dqs differential slew rate. note for dq and dm signals, v re f(dc)=vref dq (dc). for input only pins except reset, vref(dc)=vref ca (dc). 18. start of internal write transa ction is defined as follows: for bl8 (fixed by mrs and on - the - fly): rising clock edge 4 clock cycles after wl. for bc4 (on - the - fly): rising clock edge 4 clock cycles after wl. for bc4 (fixed by mrs): rising clock edge 2 clock cycles after wl. 19. the maximum p reamble is bound by t lz (dqs) max on the left side and t dqsck (max) on the right side. 20. cke is allowed to be registered low while operations such as row activation, precharge, autoprecharge or refresh are in progress, but power - down idd spec will not be appl ied until finishing those operations. 21. although cke is allowed to be registered low after a refresh command once t refpden (min) is satisfied, there are cases where additional time such as t xpdll (min) is also required. 22. defined between end of mpr read burst a nd mrs which reloads mpr or disables mpr function. ddr3 (l) 2 gb sdram nt5c b( c ) 256 m8 f n / nt5cb(c) 128 m16 f p version 1. 6 150 nanya technology cooperation ? 0 4 / 201 4 all rights reserved. 23. one zqcs command can effectively correct a minimum of 0.5% (zqcorrection) of ron and rtt impedance error within 64 nck for all speed bins assuming the maximum sensitivities specified in the output driver voltage and temperature sensitivity and odt voltage and temperature sensitivity tables. the appropriate interval between zqcs commands can be determined from these tables and other application - specific parameters. one method for calculating the interva l between zqcs commands, given the temperature ( tdriftrate) and voltage (vdrift rate) drift rates that the sdram is subject to in the application, is illustrated. the interval could be defined by the following f ormula: zqcorrection / [(tsens x tdriftrate) + (vsens x vdriftrate)] where tsens = max(drttdt, drondtm) and vsens = max(drttdv, drondvm) define the sdram temperature and voltage sensitivities. for example, if tsens = 1.5%/c, vsens = 0.15%/mv, tdriftrate = 1 c/sec and vdriftrate = 15mv/sec, then the i nterval between zqcs commands is calculated as 0.5 / [(1.5x1)+(0.15x15)] = 0.133 ~ 128ms 24. n = from 13 cycles to 50 cycles. this row defines 38 parameters. 25. t ch (abs) is the absolute instantaneous clock high pulse width, as measured from one rising edge to the following falling edge. 26. t cl (abs) is the absolute instantaneous clock low pulse width, as measured from one falling edge to the following rising edge. 27. the t is (base) ac150 specifications are adjusted from the t is (base) specification by adding an additional 100ps of derating to accommodate for the lower altemate threshold of 150mv and another 25ps to account for the earlier reference point [(175mv C 150mv) / 1v/ns] . ddr3 (l) 2 gb sdram nt5c b( c ) 256 m8 f n / nt5cb(c) 128 m16 f p version 1. 6 151 nanya technology cooperation ? 0 4 / 201 4 all rights reserved. address / command setup, hold, and derating for all input signals the total tis (setup time) a nd tih (hold time) required is calculated by adding the data sheet tis (base) and tih (base) and tih (base) value to the delta tis and delta tih derating value respectively. example: tis (total setup time) = tis (base) + delta tis setup ( tis ) nominal slew ra te for a rising signal is defined as the slew rate between the last crossing of vref(dc) and the first crossing of vih(ac)min. setup ( tis ) nominal slew rate for a falling signal is defined as the slew rate between the last crossing of vref(dc) and the firs t crossing of vil(ac)max. if the actual signal is always earlier than the nominal slew rate line between shaded vref(dc) to ac region, use nominal slew rate for derating value. if the actual signal is later than the nominal slew rate line anywhere betwee n shaded vref(dc) to ac region, the slew rate of the tangent line to the actual signal from the ac level to dc level is used for derating value. hold ( tih ) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of vi l(dc)max and the first crossing of vref(dc). hold ( tih ) nominal slew rate for a falling signal is defined as the slew rate between the last crossing of vih(dc)min and the first crossing of vref(dc). if the actual signal is always later than the nominal sle w rate line between shaded dc to vref(dc) region, use nominal slew rate for derating value. if the actual signal is earlier than the nominal slew rate line any where between shaded dc to vref(dc) region, the slew rate of a tangent line to the actual si gnal from the dc level to vref(dc) level is used for derating value. for a valid transition the input signal has to remain above/below vih/il(ac) for some time tvac . although for slow slew rates the total setup time might be negative (i.e. a valid input si gnal will not have reached vih/il(ac) at the time of the rising clock transition) a valid input signal is still required to complete the transition and reach vih/il(ac). add/cmd setup and hold base - values for 1v/ns grade symbol reference 800 1066 1333 1600 1866 2133 unit notes ddr3 tis(base) ac175 vih/l(ac) 200 125 65 45 - - ps 1 tis(base) ac150 vih/l(ac) 350 275 190 170 - - ps 1 tis(base) ac135 vih/l(ac) - - - - 65 60 ps 1 tis(base) ac125 vih/l(ac) - - - - 150 135 ps 1 tih(base) dc100 vih/l(dc) 27 5 200 140 120 100 95 ps 1 ddr3 l tis(base) ac160 vih/l(ac) 215 140 80 60 - - ps 1 tis(base) ac135 vih/l(ac) 365 290 205 185 65 - ps 1,2 tis(base) ac125 vih/l(ac) - - - - 150 - ps 1,3 tih(base) dc90 vih/l(ac) 285 210 150 130 110 - ps 1 note 1 (ac/dc referenced for 1 v/ns address/command slew rate and 2 v/ns differential ck - ?? slew rate) note 2 the tis(base) ac135 specifications are adjusted from the tis(base) ac160 specification by adding an additional 125 ps for ddr3l - 800/1066 or 100 ps for ddr3l - 133 3/1600 of derating to accommodate for the lower alternate threshold of 135 mv and another 25 ps to account for the earlier reference point [(160 mv - 135 mv) / 1 v/ns]. note 3 the tis(base) ac125 specifications are adjusted from the tis(base) ac135 specifi cation by adding an additional 75 ps for ddr3l - 1866 of derating to accommodate for the lower alternate threshold of 135 mv and another 10 ps to account for the earlier reference po int [(135 mv - 125 mv) / 1 v/ns]. ddr3 (l) 2 gb sdram nt5c b( c ) 256 m8 f n / nt5cb(c) 128 m16 f p version 1. 6 152 nanya technology cooperation ? 0 4 / 201 4 all rights reserved. derating values ddr3l - 800/1066/1333/1600 tis/tih - ac/dc based ac160 threshold ddr3l ac160 threshold - > vih(acac)=vref(dc)+160 mv, vil(ac)=vref(dc) - 160 mv ck, ?? differential slew rate 4.0 v/ns 3.0 v/ns 2.0 v/ns 1.8 v/ns 1.6 v/ns 1.4 v/ns 1.2 v/ns 1.0 v/ns tis tih tis tih tis tih ti s tih tis tih tis tih tis tih tis tih cmd/add slew rate v/ns 2 80 45 80 45 80 45 88 53 96 61 104 69 112 79 120 95 1.5 53 30 53 30 53 30 61 38 69 46 77 54 85 64 93 80 1 0 0 0 0 0 0 8 8 16 16 24 24 32 34 40 50 0.9 - 1 - 3 - 1 - 3 - 1 - 3 7 5 15 13 23 21 31 31 39 47 0.8 - 3 - 8 - 3 - 8 - 3 - 8 5 1 13 9 21 17 29 27 37 43 0.7 - 5 - 13 - 5 - 13 - 5 - 13 3 - 5 11 3 19 11 27 21 35 37 0.6 - 8 - 20 - 8 - 20 - 8 - 20 0 - 12 8 - 4 16 4 24 14 32 30 0.5 - 20 - 30 - 20 - 30 - 20 - 30 - 12 - 22 - 4 - 14 4 - 6 12 4 20 20 0.4 - 40 - 45 - 4 0 - 45 - 40 - 45 - 32 - 37 - 24 - 29 - 16 - 21 - 8 - 11 0 5 derating values ddr3l - 800/1066/1333/1600 tis/tih - ac/dc based ac135 threshold ddr3l alternate ac135 threshold - > vih(ac)=vref(dc)+135 mv, vil(ac)=vref(dc) - 135 mv ck, ?? differential slew rate 4.0 v/ns 3.0 v/ns 2.0 v/ns 1.8 v/ns 1.6 v/ns 1.4 v/ns 1.2 v/ns 1.0 v/ns tis tih tis tih tis tih tis tih tis tih tis tih tis tih tis tih cmd/add slew rate v/ns 2 68 45 68 45 68 45 76 53 84 61 92 69 100 79 108 9 5 1.5 45 30 45 30 45 30 53 38 61 46 69 54 77 64 85 80 1 0 0 0 0 0 0 8 8 16 16 24 24 32 34 40 50 0.9 2 - 3 2 - 3 2 - 3 10 5 18 13 26 21 34 31 42 47 0.8 3 - 8 3 - 8 3 - 8 11 1 19 9 27 17 35 27 43 43 0.7 6 - 13 6 - 13 6 - 13 14 - 5 22 3 30 11 38 21 46 37 0. 6 9 - 20 9 - 20 9 - 20 17 - 12 25 - 4 33 4 41 14 49 30 0.5 5 - 30 5 - 30 5 - 30 13 - 22 21 - 14 29 - 6 37 4 45 20 0.4 - 3 - 45 - 3 - 45 - 3 - 45 6 - 37 14 - 29 22 - 21 30 - 11 38 5 ddr3 (l) 2 gb sdram nt5c b( c ) 256 m8 f n / nt5cb(c) 128 m16 f p version 1. 6 153 nanya technology cooperation ? 0 4 / 201 4 all rights reserved. derating values ddr3l - 1866 tis/tih - ac/dc based ac125 threshold ddr3l alternate ac125 th reshold - > vih(ac)=vref(dc)+125 mv, vil(ac)=vref(dc) - 125 mv ck, ?? differential slew rate 4.0 v/ns 3.0 v/ns 2.0 v/ns 1.8 v/ns 1.6 v/ns 1.4 v/ns 1.2 v/ns 1.0 v/ns tis tih tis tih tis tih tis tih tis tih tis tih tis tih tis tih cmd/add slew rate v/ns 2 63 45 63 45 63 45 71 53 79 61 87 69 95 79 103 95 1.5 42 30 42 30 42 30 50 38 58 46 66 54 74 64 82 80 1 0 0 0 0 0 0 8 8 16 16 24 24 32 34 40 50 0.9 3 - 3 3 - 3 3 - 3 11 5 19 13 27 21 35 31 43 47 0.8 6 - 8 6 - 8 6 - 8 14 1 22 9 30 17 38 2 7 46 43 0.7 10 - 13 10 - 13 10 - 13 18 - 5 26 3 34 11 42 21 50 37 0.6 16 - 20 16 - 20 16 - 20 24 - 12 32 4 40 - 4 48 14 56 30 0.5 15 - 30 15 - 30 15 - 30 23 - 22 31 - 14 39 - 6 47 4 55 20 0.4 13 - 45 13 - 45 13 - 45 21 - 37 29 - 29 37 - 21 45 - 11 53 5 derating valu es ddr3 - 800/1066/1333/1600 tis/tih - ac/dc based ac175 threshold ddr3 ac175 threshold - > vih(ac)=vref(dc)+175mv, vil(ac)=vref(dc) - 175mv ck, ?? differential slew rate 4.0 v/ns 3.0 v/ns 2.0 v/ns 1.8 v/ns 1.6 v/ns 1.4 v/ns 1.2 v/ns 1.0 v/ns tis tih t is tih tis tih tis tih tis tih tis tih tis tih tis tih cmd/add slew rate v/ns 2 88 50 88 50 88 50 96 58 104 66 112 74 120 84 128 100 1.5 59 34 59 34 59 34 67 42 75 50 83 58 91 68 99 84 1 0 0 0 0 0 0 8 8 16 16 24 24 32 34 40 50 0.9 - 2 - 4 - 2 - 4 - 2 - 4 6 4 14 12 22 20 30 30 38 46 0.8 - 6 - 10 - 6 - 10 - 6 - 10 2 - 2 10 6 18 14 26 24 34 40 0.7 - 11 - 16 - 11 - 16 - 11 - 16 - 3 - 8 5 0 13 8 21 18 29 34 0.6 - 17 - 26 - 17 - 26 - 17 - 26 - 9 - 18 - 1 - 10 7 - 2 15 8 23 24 0.5 - 35 - 40 - 35 - 40 - 35 - 40 - 27 - 32 - 19 - 24 - 11 - 16 - 2 - 6 5 10 0.4 - 62 - 60 - 62 - 60 - 62 - 60 - 54 - 52 - 46 - 44 - 38 - 36 - 30 - 26 - 22 - 10 ddr3 (l) 2 gb sdram nt5c b( c ) 256 m8 f n / nt5cb(c) 128 m16 f p version 1. 6 154 nanya technology cooperation ? 0 4 / 201 4 all rights reserved. derating values ddr3 - 800/1066/1333/1600 tis/tih - ac/dc based ac150 threshold ddr3 alternate ac150 threshold - > vih(ac)=vref(dc)+150mv, vil(ac)=vref(dc) - 150mv ck, ?? differential slew rate 4.0 v/ns 3.0 v/ns 2.0 v/ns 1.8 v/ns 1.6 v/ns 1.4 v/ns 1.2 v/ns 1.0 v/ns tis tih tis tih tis tih tis tih tis tih tis tih tis tih tis tih cmd/add slew rate v/ns 2 75 50 75 50 75 50 83 58 91 66 99 74 107 84 1 15 100 1.5 50 34 50 34 50 34 58 42 66 50 74 58 82 68 90 84 1 0 0 0 0 0 0 8 8 16 16 24 24 32 34 40 50 0.9 0 - 4 0 - 4 0 - 4 8 4 16 12 24 20 32 30 40 46 0.8 0 - 10 0 - 10 0 - 10 8 - 2 16 6 24 14 32 24 40 40 0.7 0 - 16 0 - 16 0 - 16 8 - 8 16 0 24 8 32 18 40 34 0.6 - 1 - 26 - 1 - 26 - 1 - 26 7 - 18 15 - 10 23 - 2 31 8 39 24 0.5 - 10 - 40 - 10 - 40 - 10 - 40 - 2 - 32 6 - 24 14 - 16 22 - 6 30 10 0.4 - 25 - 60 - 25 - 60 - 25 - 60 - 17 - 52 - 9 - 44 - 1 - 36 7 - 26 15 - 10 derating values ddr3 - 1866/2133 tis/tih - ac/dc based ac135 threshol d ddr3 alternate ac135 threshold - > vih(ac)=vref(dc)+135mv, vil(ac)=vref(dc) - 135mv ck, ?? differential slew rate 4.0 v/ns 3.0 v/ns 2.0 v/ns 1.8 v/ns 1.6 v/ns 1.4 v/ns 1.2 v/ns 1.0 v/ns tis tih tis tih tis tih tis tih tis tih tis tih tis tih tis tih cmd/add slew rate v/ns 2 68 50 68 50 68 50 76 58 84 66 92 74 100 84 108 100 1.5 45 34 45 34 45 34 53 42 61 50 69 58 77 68 85 84 1 0 0 0 0 0 0 8 8 16 16 24 24 32 34 40 50 0.9 2 - 4 2 - 4 2 - 4 10 4 18 12 26 20 34 30 42 46 0.8 3 - 10 3 - 1 0 3 - 10 11 - 2 19 6 27 14 35 24 43 40 0.7 6 - 16 6 - 16 6 - 16 14 - 8 22 0 30 8 38 18 46 34 0.6 9 - 26 9 - 26 9 - 26 17 - 18 25 - 10 33 - 2 41 8 49 24 0.5 5 - 40 5 - 40 5 - 40 13 - 32 21 - 24 29 - 16 37 - 6 45 10 0.4 - 3 - 60 - 3 - 60 - 3 - 60 6 - 52 14 - 44 22 - 36 30 - 26 3 8 - 10 ddr3 (l) 2 gb sdram nt5c b( c ) 256 m8 f n / nt5cb(c) 128 m16 f p version 1. 6 155 nanya technology cooperation ? 0 4 / 201 4 all rights reserved. derating values ddr3 - 1866/2133 tis/tih - ac/dc based ac125 threshold ddr3 alternate ac125 threshold - > vih(ac)=vref(dc)+125mv, vil(ac)=vref(dc) - 125mv ck, ?? differential slew rate 4.0 v/ns 3.0 v/ns 2.0 v/ns 1.8 v/ns 1.6 v/ns 1.4 v/ns 1.2 v/ns 1.0 v/ns tis tih tis tih tis tih tis tih tis tih tis tih tis tih tis tih cmd/add slew rate v/ns 2 63 50 63 50 63 50 71 58 79 66 87 74 95 84 103 10 0 1.5 42 34 42 34 42 34 50 42 58 50 66 58 74 68 82 84 1 0 0 0 0 0 0 8 8 16 16 24 24 32 34 40 50 0.9 4 - 4 4 - 4 4 - 4 12 4 20 12 28 20 36 30 44 46 0.8 6 - 10 6 - 10 6 - 10 14 - 2 22 6 30 14 38 24 46 40 0.7 11 - 16 11 - 16 11 - 16 19 - 8 27 0 35 8 43 18 51 3 4 0.6 16 - 26 16 - 26 16 - 26 24 - 18 32 - 10 40 - 2 48 8 56 24 0.5 15 - 40 15 - 40 15 - 40 23 - 32 31 - 24 39 - 16 47 - 6 55 10 0.4 13 - 60 13 - 60 13 - 60 21 - 52 29 - 44 37 - 36 45 - 26 53 - 10 ddr3 (l) 2 gb sdram nt5c b( c ) 256 m8 f n / nt5cb(c) 128 m16 f p version 1. 6 156 nanya technology cooperation ? 0 4 / 201 4 all rights reserved. required time t vac above vih( ac ) {below vil( ac )} for add/cmd transition s lew rate [v/ns] ddr3 ddr3l unit 800/1066/1333/1600 1866/2133 800/1066/1333/1600 1866 175mv [ps] 150mv[ps] 135mv [ps] 125mv [ps] 160 mv [ps] 135 mv [ps] 135 mv [ps] 125 mv [ps] > 2.0 75 175 168 173 200 213 200 205 ps 2.0 57 170 168 173 200 213 200 2 05 ps 1.5 50 167 145 152 173 190 178 184 ps 1.0 38 130 100 110 120 145 133 143 ps 0.9 34 113 85 96 102 130 118 129 ps 0.8 29 93 66 79 80 111 99 111 ps 0.7 22 66 42 56 51 87 75 89 ps 0.6 note 30 10 27 13 55 43 59 ps 0.5 note note note note note 10 no te 18 ps < 0.5 note note note note note 10 note 18 ps note rising input signal shall become equal to or greater than vih(ac) level and falling input signal shall become equal to or less than vil(ac) level. ddr3 (l) 2 gb sdram nt5c b( c ) 256 m8 f n / nt5cb(c) 128 m16 f p version 1. 6 157 nanya technology cooperation ? 0 4 / 201 4 all rights reserved. data setup, hold, and slew rate de - rating fo r all input signals the total tds (setup time) and tdh (hold time) required is calculated by adding the data sheet td s (base) and tdh(base) value to the delta tds and delta tdh derating value respectively. example: tds (total setup time) = tds(base) + delt a tds setup (tds) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of vref(dc) and the first crossing of vih(ac)min. setup (tds) nominal slew rate for a falling signal is defined as the slew rate between the last crossing of vref(dc) and the first crossing of vil(ac)max. if the actual signal is always earlier than the nominal slew rate line between shaded vref(dc) to ac region, use nominal slew rate for derating value. if the actual signal is later than the nomi nal slew rate line anywhere between shaded vref(dc) to ac region, the slew rate of the tangent line to the actual signal from the ac level to dc level is used for derating value. hold (tdh) nominal slew rate for a rising signal is defined as the slew ra te between the last crossing of vil(dc)max and the first crossing of vref(dc). hold (tdh) nominal slew rate for a falling signal is defined as the slew rate between the last crossing of vih(dc)min and the first crossing of vref(dc). if the actual signal is always later than the nominal slew rate line between shaded dc level to vref(dc) region, use nominal slew rate for derating value. if the actual signal is earlier than the nominal slew rate line anywhere between shaded dc to vref(dc) region, the slew rate of a tangent line to the actual signal from the dc level to vref(dc) level is used for derating value. for a valid transition the input signal has to remain above/below vih/il(ac) for some time tvac. although for slow slew rates the total setup time might be negative (i.e. a valid input signal will not have reached vih/il(ac) at the time of the rising clock transition) a valid input signal is still required to complete the transition and reach vih/i l(ac). for slew rates in between the values listed i n the following tables, the derating values may be obtained by linear interpolation. these values are typically not subject to production test. they are verified by design and characterization. derating values ddr3l - 800/1066 tds/tdh - ac/dc based ac160 th reshold ddr3 l ac160 threshold - > vih(ac)=vref(dc)+160mv, vil(ac)=vref(dc) - 160mv dqs , ??? differential slew rate 4.0 v/ns 3.0 v/ns 2.0 v/ns 1.8 v/ns 1.6 v/ns 1.4 v/ns 1.2 v/ns 1.0 v/ns t d s t d h t d s t d h t d s t d h t d s t d h t d s t d h t d s t d h t d s t d h t d s t d h dq slew rate v/ns 2 80 45 80 45 80 45 - - - - - - - - - - 1.5 53 30 53 30 53 30 61 38 - - - - - - - - 1 0 0 0 0 0 0 8 8 16 16 - - - - - - 0.9 - - - 1 - 3 - 1 - 3 7 5 15 13 23 21 - - - - 0.8 - - - - - 3 - 8 5 1 13 9 21 17 29 27 - - 0.7 - - - - - - 3 - 5 11 3 19 11 27 21 35 37 0.6 - - - - - - - - 8 - 4 16 4 24 14 32 30 0.5 - - - - - - - - - - 4 - 6 12 4 20 20 0.4 - - - - - - - - - - - - - 8 - 11 0 5 note1: cell contents shaded in gray are defined as not supported. ddr3 (l) 2 gb sdram nt5c b( c ) 256 m8 f n / nt5cb(c) 128 m16 f p version 1. 6 158 nanya technology cooperation ? 0 4 / 201 4 all rights reserved. derating values ddr3l - 800/1066/1333/1600 tds/tdh - ac/dc based ac135 / threshold ddr3 l alternate ac135 threshold - > vih(ac)=vref(dc)+135mv, vil(ac)=vref(dc) - 135mv dqs , ??? differential slew rate 4.0 v/ns 3.0 v/ns 2.0 v/ns 1.8 v/ns 1.6 v/ns 1.4 v/ns 1.2 v/ns 1.0 v/ns t d s t d h t d s t d h t d s t d h t d s t d h t d s t d h t d s t d h t d s t d h t d s t d h dq slew rate v/ns 2 45 68 45 68 45 - - - - - - - - - - 1.5 45 30 45 3 0 45 30 53 38 - - - - - - - - 1 0 0 0 0 0 0 8 8 16 16 - - - - - - 0.9 - - 2 - 3 2 - 3 10 5 18 13 26 21 - - - - 0.8 - - - - 3 - 8 11 1 19 9 27 17 35 27 - - 0.7 - - - - - - 14 - 5 22 3 30 11 38 21 46 37 0.6 - - - - - - - - 25 - 4 33 4 41 14 49 30 0.5 - - - - - - - - - - 29 - 6 37 4 45 20 0.4 - - - - - - - - - - - - 30 - 11 38 5 note1: cell contents shaded in gray are defined as not supported. derating values ddr3 l - 1866 tds/tdh - ac/dc based ac130 threshold ddr3 l alternate ac130 threshold - > vih( ac)=vref(dc)+130mv, vil(ac)=vref(dc) - 130mv dqs , ??? differential slew rate 8 .0 v/ns 7 .0 v/ns 6 .0 v/ns 5 .0 v/ns 4.0 v/ns 3.0 v/ns 2.0 v/ns 1.8 v/ns 1.6 v/ns 1.4 v/ns 1.2 v/ns 1.0 v/ns tds tdh tds tdh tds tdh tds tdh tds tdh tds tdh tds t dh tds tdh tds tdh tds tdh tds tdh tds tdh dq slew rate v/ns 4 33 23 33 23 33 23 - - - - - - - - - - - - - - - - - - 3.5 28 19 28 19 28 19 28 19 - - - - - - - - - - - - - - - - 3 22 15 22 15 22 15 22 15 22 15 - - - - - - - - - - - - - - 2. 5 - - 13 9 13 9 13 9 13 9 13 9 - - - - - - - - - - - - 2 - - - - 0 0 0 0 0 0 0 0 0 0 - - - - - - - - - - 1.5 - - - - - - - 22 - 15 - 22 - 15 - 22 - 15 - 22 - 15 - 14 - 7 - - - - - - - - 1 - - - - - - - - - 65 - 45 - 65 - 45 - 65 - 45 - 57 - 37 - 49 - 29 - - - - - - 0. 9 - - - - - - - - - - - 62 - 48 - 62 - 48 - 54 - 40 - 46 - 32 - 38 - 24 - - - - 0.8 - - - - - - - - - - - - - 61 - 53 - 53 - 45 - 45 - 37 - 37 - 29 - 29 - 19 - - 0.7 - - - - - - - - - - - - - - - 49 - 50 - 41 - 42 - 33 - 34 - 25 - 24 - 17 - 8 0.6 - - - - - - - - - - - - - - - - - 37 - 49 - 29 - 41 - 21 - 31 - 13 - 15 0.5 - - - - - - - - - - - - - - - - - - - 31 - 51 - 23 - 41 - 15 - 25 0.4 - - - - - - - - - - - - - - - - - - - - - 28 - 56 - 20 - 40 note1: cell contents shaded in gray are defined as not supported. ddr3 (l) 2 gb sdram nt5c b( c ) 256 m8 f n / nt5cb(c) 128 m16 f p version 1. 6 159 nanya technology cooperation ? 0 4 / 201 4 all rights reserved. derating values ddr3 - 800/1 066 tds/tdh - ac/dc based ac175 threshold ddr3 ac1 75 threshold dqs , ??? differential slew rate 4.0 v/ns 3.0 v/ns 2.0 v/ns 1.8 v/ns 1.6 v/ns 1.4 v/ns 1.2 v/ns 1.0 v/ns t d s t d h t d s t d h t d s t d h t d s t d h t d s t d h t d s t d h t d s t d h t d s t d h dq slew rate v/ns 2 50 88 50 88 50 - - - - - - - - - - 1.5 59 34 59 3 4 59 34 67 42 - - - - - - - - 1 0 0 0 0 0 0 8 8 16 16 - - - - - - 0.9 - - - 2 - 4 - 2 - 4 6 4 14 12 22 20 - - - - 0.8 - - - - - 6 - 10 2 - 2 10 6 18 14 26 24 - - 0.7 - - - - - - - 3 - 8 5 0 13 8 21 18 29 34 0.6 - - - - - - - - - 1 - 10 7 - 2 15 8 23 24 0.5 - - - - - - - - - - - 11 - 16 - 2 - 6 5 10 0.4 - - - - - - - - - - - - - 30 - 26 - 22 - 10 note1: cell contents shaded in gray are defined as not supported. derating values ddr3 - 800/1066/1333/1600 tds/tdh - ac/dc based ac150 threshold ddr3 ac1 50 threshol d dqs , ??? differential slew rate 4.0 v/ns 3.0 v/ns 2.0 v/ns 1.8 v/ns 1.6 v/ns 1.4 v/ns 1.2 v/ns 1.0 v/ns t d s t d h t d s t d h t d s t d h t d s t d h t d s t d h t d s t d h t d s t d h t d s t d h dq slew rate v/ns 2 50 75 50 75 50 - - - - - - - - - - 1.5 5 0 34 50 34 50 34 58 42 - - - - - - - - 1 0 0 0 0 0 0 8 8 16 16 - - - - - - 0.9 - - 0 - 4 0 - 4 8 4 16 12 24 20 - - - - 0.8 - - - - 0 - 10 8 - 2 16 6 24 14 32 24 - - 0.7 - - - - - - 8 - 8 16 0 24 8 32 18 40 34 0.6 - - - - - - - - 15 - 10 23 - 2 31 8 39 2 4 0.5 - - - - - - - - - - 14 - 16 22 - 6 30 10 0.4 - - - - - - - - - - - - 7 - 26 15 - 10 note1: cell contents shaded in gray are defined as not supported. ddr3 (l) 2 gb sdram nt5c b( c ) 256 m8 f n / nt5cb(c) 128 m16 f p version 1. 6 160 nanya technology cooperation ? 0 4 / 201 4 all rights reserved. derating values ddr3 - 1866/2133 tds/tdh - ac/dc based ac135 threshold ddr3 alternate ac135 th reshold - > vih(ac)=vref(dc)+135mv, vil(ac)=vref(dc) - 135mv alternate dc100 threshold - > vih(dc)=vref(dc)+100mv, vil(dc)=vref(dc) - 100mv dqs , ??? differential slew rate 8 .0 v/ns 7 .0 v/ns 6 .0 v/ns 5 .0 v/ns 4.0 v/ns 3.0 v/ns 2.0 v/ns 1.8 v/ns 1.6 v/ns 1.4 v/ns 1.2 v/ns 1.0 v/ns tds tdh tds tdh tds tdh tds tdh tds tdh tds tdh tds tdh tds tdh tds tdh tds tdh tds tdh tds tdh dq slew rate v/ns 4 34 25 34 25 34 25 - - - - - - - - - - - - - - - - - - 3.5 29 21 29 21 29 21 29 21 - - - - - - - - - - - - - - - - 3 23 17 23 17 23 17 23 17 23 17 - - - - - - - - - - - - - - 2.5 - - 14 10 14 10 14 10 14 10 14 10 - - - - - - - - - - - - 2 - - - - 0 0 0 0 0 0 0 0 0 0 - - - - - - - - - - 1.5 - - - - - - - 23 - 17 - 23 - 17 - 23 - 17 - 23 - 17 - 1 5 - 9 - - - - - - - - 1 - - - - - - - - - 68 - 50 - 68 - 50 - 68 - 50 - 60 - 42 - 52 - 34 - - - - - - 0.9 - - - - - - - - - - - 66 - 54 - 66 - 54 - 58 - 46 - 50 - 38 - 42 - 30 - - - - 0.8 - - - - - - - - - - - - - 64 - 60 - 56 - 52 - 48 - 44 - 40 - 36 - 32 - 26 - - 0.7 - - - - - - - - - - - - - - - 53 - 59 - 45 - 51 - 37 - 43 - 29 - 33 - 21 - 17 0.6 - - - - - - - - - - - - - - - - - 43 - 61 - 35 - 53 - 27 - 43 - 19 - 27 0.5 - - - - - - - - - - - - - - - - - - - 39 - 66 - 31 - 56 - 23 - 40 0.4 - - - - - - - - - - - - - - - - - - - - - 38 - 76 - 30 - 60 note1: cell contents shaded in gray are defined as not supported. derating values ddr3 - 800/1066/1333/1600 tds/tdh - ac/dc based ac135 threshold ddr3 alternate ac135 threshold - > vih(ac)=vref(dc)+135mv, vil(ac)=vref(dc) - 135mv alternate dc100 thresh old - > vih(dc)=vref(dc)+100mv, vil(dc)=vref(dc) - 100mv dqs , ??? differential slew rate 4.0 v/ns 3.0 v/ns 2.0 v/ns 1.8 v/ns 1.6 v/ns 1.4 v/ns 1.2 v/ns 1.0 v/ns t d s t d h t d s t d h t d s t d h t d s t d h t d s t d h t d s t d h t d s t d h t d s t d h dq slew rat e v/ns 2 68 50 68 50 68 50 - - - - - - - - - - 1.5 45 34 45 34 45 34 53 42 - - - - - - - - 1 0 0 0 0 0 0 8 8 16 16 - - - - - - 0.9 - - 2 - 4 2 - 4 10 4 18 12 26 20 - - - - 0.8 - - - - 3 - 10 11 - 2 19 6 27 14 35 24 - - 0.7 - - - - - - 14 - 8 22 0 30 8 38 18 46 34 0.6 - - - - - - - - 25 - 10 33 - 2 41 8 49 24 0.5 - - - - - - - - - - 29 - 16 37 - 6 45 10 0.4 - - - - - - - - - - - - 30 - 26 38 - 10 note1: cell contents shaded in gray are defined as not supported. ddr3 (l) 2 gb sdram nt5c b( c ) 256 m8 f n / nt5cb(c) 128 m16 f p version 1. 6 16 1 nanya technology cooperation ? 0 4 / 201 4 all rights reserved. required time t vac above vih( ac ) {below vil( ac )} for dq transition slew rate [v/ns] ddr3 ddr3l unit 800/1066 800/1066/ 1333/1600 800/1066/ 1333/1600 1866 2133 800/106 6 800/1066/ 1333/1600 1866 175mv [ps] 150mv[ps] 135mv [ps] 1 3 5mv [ps] 1 35 mv [ps] 1 60 mv [ps] 135 mv [ps] 1 30 mv [ps] > 2.0 75 105 113 93 73 165 113 95 ps 2.0 57 105 113 93 73 165 113 95 ps 1.5 50 80 90 70 50 138 90 73 ps 1.0 38 30 45 25 5 85 45 30 ps 0.9 34 13 30 note note 67 30 16 ps 0.8 29 note 11 note note 45 11 note ps 0.7 note note note - - 16 note - ps 0.6 note n ote note - - note note - ps 0.5 note note note - - note note - ps < 0.5 note note note - - note note - ps note rising input signal shall become equal to or greater than vih(ac) level and falling input signal shall become equal to or less than vil(ac) le vel. ddr3 (l) 2 gb sdram nt5c b( c ) 256 m8 f n / nt5cb(c) 128 m16 f p version 1. 6 162 nanya technology cooperation ? 0 4 / 201 4 all rights reserved. revision history version page modified description released 1.0 - - draft release 12 / 2011 1.0 - - revised table 1 and ordering information 05/ 2012 1.0 - - revised x8/78 balls package size 06/ 2012 1.0 - - added idd specification at 1.5v to t he page 108 and 109 tables 07/ 2012 1.0 - - added 13 and 14 to mr0 cas latency table 08/ 2012 1.0 - - revised table 3 and ordering information 09/ 2012 1.0 - - updated 2133 ac timing spec 10/ 2012 1.0 - - re - move speed 1066 and 1333 spec 12/ 2012 1.0 - - added speed 1866 spec information 01/ 2013 1.0 - - modified mr2 function 02/ 2013 1.0 - - modified idd spec 02/ 2013 1.0 - - added rs ( reduced standaby ) part numbers 02/ 2013 1.0 - - modified part numbers 03/ 2013 1.0 - - added automotive garde 3 part num ber 04/ 2013 1.0 - - added trfc spec 05/ 2013 1.1 p1 renew the first page. 06/ 2013 all - 1. remove on page xxx 2. follow ntc s data center to change the revision rule p3 ordering information add part number nt5cb128m16fp - dih . p4 part number na ming rule special type option 1. add h = automotive grade 2 2. modify a = automotive 3 (was: a = automotive) p5 - 11 fundamental ac specifications 1. make all options follow jedec standards. 2. add 800, 1066 and 1333 specifications. p13 - 14 package outline drawing 1. add side view of package to pod 2. redraw the ballout p24,27,30,32 mr0,1,2,3 redraw the mr functions p89 absolute maximum dc rating s follow jedec specifications ? vdd: - 0.4v ~ 1.8v (was: - 0.4v ~ 1.975v) ? vddq: - 0.4v ~ 1.8v (was: - 0.4v ~ 1.975v) ? vin,vout: - 0.4v ~ 1.8v (was: - 0.4v ~ 1.975v) p90 temperature spec automatic grade 3: - 40 to 85 (was: - 40 to 95) p92 - 123 all 1. make all specifications follow jedec specifications 2. add ddr3(l) 800, 1066 and 1333 specifications p124 - 136 idd specifications 1. add idd test conditions 2. add iddq2nt specifications p137 - 143 timing specifications 1. make all specifications follow jedec specifications 2. add ddr3(l) 800, 1066 and 1333 specifications p146 - 156 derating table 1. make all specifications follow jedec specifications 2. a dd ddr3(l) 800, 1066 and 1333 specifications 1.2 p14 96 ballout update pod spec to 12mm (was: 11.2mm caused by typo) 06/ 2013 p24,27,30,32 mr add notes below the mr tables p1,p90 temperature spec 1. automotive grade 3: - 40 ~ 95 (was: - 40~85) 2. a dd automot ive grade 2 spec on page 90. p147 - 150, 152 - 155 tis/tih/tds/tdh derating table add dc conditions p152 data setup,hold c orrect the typo in 1 st paragraph: td s (base) and tdh(base) , was: tdh(base) and tdh(base) 1.3 p3 ordering info add part number: nt5c c128m16fp - dia nt5cc128m16fp - dih 07/ 2013 1.4 all - renew the format. 09/ 2013 1.5 p2,4,12 4 , 125, 1 38 ddr3l - 1866 1. add ddr3l - 1866 part number and specifications. 2. update idd spec. 12/2013 1.6 p1,4 v oltage backward compatible 1. temperature range: add part number s code 2. note 4: enhance the statement of voltage backward compatible. 3. commercial grade (was: standard grade) 04/201 4 p19 cas latency c orrect the description: b it a 2, a4 ~a 6 (was: bit a9~a11) p45, p123, 124 s elf refresh emphasize the difference among the grades about s elf refresh temperature range ddr3 (l) 2 gb sdram nt5c b( c ) 256 m8 f n / nt5cb(c) 128 m16 f p version 1. 6 163 nanya technology cooperation ? 0 4 / 201 4 all rights reserved. http://www.nanya.com/ |
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